39 lines
1.1 KiB
Plaintext
39 lines
1.1 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {type=spice_parameters
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template="name=s1
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sigma=1u
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param=W
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value=10u
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"
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format=".param @param = agauss(@value , @sigma , 1)"}
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V {}
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S {}
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E {}
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L 4 0 -10 140 -10 {}
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T { PARAMETER
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name: @param
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value: @value
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1-sigma: @sigma} 5 -25 0 0 0.3 0.3 {}
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