70 lines
1.9 KiB
Plaintext
70 lines
1.9 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {type=package
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spice_ignore=true
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verilog_ignore=true
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tedax_ignore=true
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template="
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-- THIS IS A TEMPLATE, REPLACE WITH ACTUAL CODE OR REMOVE INSTANCE!!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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package aaa is
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type real_vector is array(natural range <>) of real;
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constant dx : real := 0.001 ;
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procedure assegna(
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signal A : inout real;
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signal A_OLD : in real;
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A_VAL : in real
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);
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end aaa; -- end package declaration
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package body aaa is
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procedure assegna(
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signal A : inout real;
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signal A_OLD : in real;
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A_VAL : in real ) is
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constant tdelay: time := 0.01 ns;
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begin
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if (A /= A_VAL) then
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A <= A_OLD+dx, A_VAL after tdelay;
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end if;
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end assegna;
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end aaa; -- end package body
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"}
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V {}
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S {}
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E {}
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L 4 0 -10 355 -10 {}
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T {PACKAGE} 5 -25 0 0 0.3 0.3 {}
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T {HIDDEN} 135 -5 0 0 0.3 0.3 {}
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