46 lines
1.7 KiB
Plaintext
46 lines
1.7 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=njfet
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format="@spiceprefix@name @pinlist @model area=@area @extra m=@m"
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template="name=J1 model=njfet area=1 m=1"
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}
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V {}
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S {}
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E {}
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L 4 5 -30 5 30 {}
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L 4 5 -20 20 -20 {}
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L 4 20 -30 20 -20 {}
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L 4 5 20 20 20 {}
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L 4 20 20 20 30 {}
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B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout}
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B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
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B 5 17.5 27.5 22.5 32.5 {name=s dir=inout}
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P 4 7 -20 0 -5 0 -5 -5 5 -0 -5 5 -5 0 -20 0 {fill=true}
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T {@spiceprefix@name} 7.5 7.5 0 0 0.2 0.2 {}
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T {D} 25 -27.5 0 0 0.15 0.15 {}
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T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance}
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T {@model} 7.5 -17.5 0 0 0.2 0.2 {}
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T {area=@area} 7.5 -5 0 0 0.2 0.2 {}
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