56 lines
1.8 KiB
Plaintext
56 lines
1.8 KiB
Plaintext
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=capacitor
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format="@name @pinlist @value m=@m"
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tedax_format="footprint @name @footprint
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value @name @value
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device @name @device
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@comptag"
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verilog_ignore=true
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vhdl_ignore=true
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template="name=C1
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m=1
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value=1p
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footprint=1206
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device=\\"ceramic capacitor\\""
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}
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V {}
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S {}
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E {}
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L 4 0 5 0 30 {}
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L 4 0 -30 0 -5 {}
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L 4 -10 -5 10 -5 {}
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L 4 -10 5 10 5 {}
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L 4 2.5 -22.5 7.5 -22.5 {}
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L 4 5 -25 5 -20 {}
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B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
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B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
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T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -5 16.25 0 1 0.2 0.2 {layer=13}
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T {@name} 15 -18.75 0 0 0.2 0.2 {}
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T {@value} 15 -6.25 0 0 0.2 0.2 {}
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T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15 hide=instance}
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T {m=@m} 15 6.25 0 0 0.2 0.2 {}
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T {@spice_get_current} -2.5 5 0 1 0.2 0.2 {layer=17}
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