38 lines
1.4 KiB
Plaintext
38 lines
1.4 KiB
Plaintext
v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=bus_tap
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template="name=l1 lab=[0]"
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format="* tap: @#1:net_name --> @#0:net_name"
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verilog_format="// tap: @#1:net_name --> @#0:net_name"
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vhdl_format="-- tap: @#1:net_name --> @#0:net_name"
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tedax_format="# tap: @#1:net_name --> @#0:net_name"}
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V {}
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S {}
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E {}
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L 1 0 0 10 -10 {}
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B 5 9.375 -10.625 10.625 -9.375 {name=tap dir=inout}
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B 5 -0.625 -0.625 0.625 0.625 {name=bus dir=inout}
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T {@lab} 12.5 -12.5 3 0 0.27 0.27 {}
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T {@#0:net_name} 31.25 -12.5 3 0 0.15 0.15 {layer=15 hide=instance}
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T {@#0:spice_get_voltage} 41.25 -12.5 3 0 0.15 0.15 {layer=15 }
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