46 lines
1.7 KiB
XML
46 lines
1.7 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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V {}
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S {}
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E {}
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T {Copyright (C) 2008 DJ Delorie (dj delorie com)
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Distributed under the terms of the GNU General Public License,
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either verion 2 or (at your choice) any later version.} 40 -150 0 0 0.4 0.4 {}
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C {ipin.sym} 280 -270 0 0 {name=p1 lab=ibcd[1:0]}
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C {opin.sym} 500 -270 0 0 {name=p2 lab=oseg[6:0] verilog_type=reg}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {code.sym} 320 -310 0 0 {name=CODE value="// Copyright (C) 2008 DJ Delorie <dj delorie com>
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// Distributed under the terms of the GNU General Public License,
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// either verion 2 or (at your choice) any later version.
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always @ (ibcd)
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begin
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case (ibcd) // abcdefg
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0 : oseg = 7'b1111110;
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1 : oseg = 7'b0110000;
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2 : oseg = 7'b1101101;
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default : oseg = 0;
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endcase
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end
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"}
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