262 lines
6.1 KiB
XML
262 lines
6.1 KiB
XML
v {xschem version=2.9.7 file_version=1.2}
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G {process
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begin
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A<='0';
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B<='0';
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wait for 1 ns;
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A<='1';
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wait for 1 ns;
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B<='1';
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wait for 1 ns;
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A<='0';
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wait for 1 ns;
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B<='0';
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wait for 1 ns;
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B<= '1';
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wait for 1 ns;
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B<= '0';
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A<= '0';
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wait for 1 ns;
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B<= '1';
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wait for 1 ns;
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A <='1';
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wait for 20 ns;
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A <= '0';
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wait for 1 ns;
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A<='Z';
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B<='Z';
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wait;
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end process;
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process
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variable n : integer := 0;
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begin
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if n = 0 then
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CK <= '0';
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n := n + 1;
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end if;
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if n = 16 then
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wait;
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end if;
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n := n + 1;
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wait for 5 ns;
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CK <= not CK;
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end process;
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process begin
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wait for 2 ns;
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WEN <='0';
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CEN <='0';
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OEN <='1';
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M <= x"00";
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ADD <="00000";
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DIN <=x"11";
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wait for 10 ns;
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ADD <="00001";
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DIN <=x"22";
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wait for 10 ns;
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ADD <="00010";
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DIN <=x"33";
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wait for 10 ns;
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ADD <="00011";
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DIN <=x"44";
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wait for 10 ns;
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WEN <='1';
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OEN <='0';
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ADD<="00000";
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wait for 10 ns;
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ADD<="00001";
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wait for 10 ns;
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ADD<="00010";
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wait for 10 ns;
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ADD<="00011";
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wait for 10 ns;
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wait;
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end process;
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}
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V {integer n = 0;
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initial begin
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$dumpfile("dumpfile.vcd");
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$dumpvars;
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A=0;
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B=0;
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#1000;
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A=1;
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#1000;
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B=1;
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#1000;
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A=0;
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#1000;
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B=0;
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#1000;
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B=1;
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#1000;
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B=0;
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A=0;
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#1000;
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B=1;
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#1000;
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A=1;
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#20000;
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A=0;
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end
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always begin
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if(n ==0 ) CK = 0;
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if(n == 23) $finish;
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n = n + 1;
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#5000;
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CK = !CK;
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end
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initial begin
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#2000;
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M ='h00; // we do not use mask bits
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// reads
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WEN=1;
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CEN=0;
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OEN=0;
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ADD=0;
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#10000;
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ADD=1;
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#10000;
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ADD=2;
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#10000;
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ADD=3;
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#10000;
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// writes
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WEN=0;
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CEN=0;
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OEN=1;
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ADD=0;
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DIN='h33;
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#10000;
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ADD=1;
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DIN='h44;
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#10000;
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ADD=2;
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DIN='h55;
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#10000;
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ADD=3;
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DIN='h66;
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#10000;
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// reads
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WEN=1;
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OEN=0;
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ADD=0;
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#10000;
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ADD=1;
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#10000;
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ADD=2;
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#10000;
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ADD=3;
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#10000;
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end
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}
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S {}
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E {}
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N 440 -350 470 -350 {lab=A}
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N 440 -310 470 -310 {lab=B}
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N 570 -330 600 -330 {lab=Y_NOR}
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N 440 -460 470 -460 {lab=A}
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N 440 -420 470 -420 {lab=B}
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N 570 -440 600 -440 {lab=Y_NAND}
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N 440 -230 470 -230 {lab=A}
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N 550 -230 580 -230 {lab=Y_INV}
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N 580 -130 610 -130 {lab=Y_XOR}
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N 450 -150 480 -150 {lab=A}
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N 450 -110 480 -110 {lab=B}
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N 810 -360 840 -360 {lab=A}
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N 920 -360 950 -360 {lab=Y_BUF}
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N 780 -90 810 -90 {lab=B}
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N 890 -90 920 -90 {lab=BN}
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C {title.sym} 160 -30 0 0 {name=l2}
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C {nr2.sym} 510 -330 0 0 {name=x1 }
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C {lab_pin.sym} 440 -350 2 1 {name=p20 lab=A}
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C {lab_pin.sym} 440 -310 2 1 {name=p1 lab=B}
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C {lab_pin.sym} 600 -330 2 0 {name=p2 lab=Y_NOR}
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C {nd2.sym} 510 -440 0 0 {name=x2 }
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C {lab_pin.sym} 440 -460 2 1 {name=p3 lab=A}
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C {lab_pin.sym} 440 -420 2 1 {name=p4 lab=B}
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C {lab_pin.sym} 600 -440 2 0 {name=p5 lab=Y_NAND}
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C {verilog_timescale.sym} 40 -570 0 0 {name=s1 timestep="1ps" precision="1ps" }
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C {lab_pin.sym} 220 -390 2 0 {name=p6 lab=A verilog_type=reg}
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C {lab_pin.sym} 220 -350 2 0 {name=p7 lab=B verilog_type=reg}
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C {iv.sym} 510 -230 0 0 {name=x3 }
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C {lab_pin.sym} 440 -230 2 1 {name=p8 lab=A}
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C {lab_pin.sym} 580 -230 2 0 {name=p9 lab=Y_INV}
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C {eo.sym} 520 -130 0 0 {name=x4}
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C {lab_pin.sym} 610 -130 2 0 {name=p10 lab=Y_XOR}
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C {lab_pin.sym} 450 -150 2 1 {name=p11 lab=A}
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C {lab_pin.sym} 450 -110 2 1 {name=p12 lab=B}
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C {bf.sym} 880 -360 0 0 {name=x5}
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C {lab_pin.sym} 810 -360 2 1 {name=p13 lab=A}
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C {lab_pin.sym} 950 -360 2 0 {name=p14 lab=Y_BUF}
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C {ff.sym} 870 -470 0 0 {name=x6}
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C {lab_pin.sym} 800 -490 2 1 {name=p15 lab=A}
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C {lab_pin.sym} 800 -450 2 1 {name=p16 lab=B}
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C {lab_pin.sym} 870 -420 2 1 {name=p17 lab=Y_NOR}
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C {lab_pin.sym} 940 -490 2 0 {name=p18 lab=Y_FF}
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C {latch.sym} 870 -250 0 0 {name=x7 del=200}
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C {lab_pin.sym} 800 -270 2 1 {name=p19 lab=A}
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C {lab_pin.sym} 800 -230 2 1 {name=p21 lab=B}
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C {lab_pin.sym} 870 -200 2 1 {name=p22 lab=Y_NOR}
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C {lab_pin.sym} 940 -270 2 0 {name=p23 lab=Y_LATCH}
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C {lab_pin.sym} 940 -230 2 0 {name=p24 lab=YN_LATCH}
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C {use.sym} 40 -670 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;}
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C {ram.sym} 840 -630 0 0 {name=xcoderam dim=5 width=8 hex=1 datafile=ram.list}
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C {lab_pin.sym} 990 -690 0 1 {name=p25 lab=DOUT[7:0]}
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C {lab_pin.sym} 690 -690 0 0 {name=p26 lab=ADD[4:0]}
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C {lab_pin.sym} 690 -650 0 0 {name=p27 lab=DIN[7:0]}
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C {lab_pin.sym} 690 -630 0 0 {name=p28 lab=WEN}
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C {lab_pin.sym} 690 -590 0 0 {name=p29 lab=OEN}
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C {lab_pin.sym} 690 -570 0 0 {name=p30 lab=CK}
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C {lab_pin.sym} 690 -610 0 0 {name=p31 lab=CEN}
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C {lab_pin.sym} 690 -670 0 0 {name=p32 lab=M[7:0]}
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C {lab_pin.sym} 220 -280 0 1 {name=p34 lab=ADD[4:0] verilog_type=reg}
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C {lab_pin.sym} 220 -320 0 1 {name=p35 lab=DIN[7:0] verilog_type=reg}
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C {lab_pin.sym} 220 -240 0 1 {name=p36 lab=WEN verilog_type=reg}
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C {lab_pin.sym} 220 -220 0 1 {name=p37 lab=OEN verilog_type=reg}
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C {lab_pin.sym} 220 -200 0 1 {name=p38 lab=CK verilog_type=reg}
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C {lab_pin.sym} 220 -260 0 1 {name=p39 lab=CEN verilog_type=reg}
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C {lab_pin.sym} 220 -300 0 1 {name=p40 lab=M[7:0] verilog_type=reg}
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C {sync_reg.sym} 840 -810 0 0 {name=x8 width=8}
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C {lab_pin.sym} 740 -840 0 0 {name=p33 lab=DIN[7:0]}
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C {lab_pin.sym} 740 -780 0 0 {name=p41 lab=CK}
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C {lab_pin.sym} 740 -800 0 0 {name=p42 lab=BN}
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C {lab_pin.sym} 740 -820 0 0 {name=p43 lab=A}
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C {lab_pin.sym} 940 -840 0 1 {name=p44 lab=DATA_OUT[7:0]}
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C {iv.sym} 850 -90 0 0 {name=x9 }
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C {lab_pin.sym} 780 -90 2 1 {name=p45 lab=B}
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C {lab_pin.sym} 920 -90 2 0 {name=p46 lab=BN}
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C {lab_pin.sym} 160 -390 2 1 {name=p47 lab=A_A verilog_type=reg}
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C {lab_pin.sym} 160 -350 2 1 {name=p48 lab=B_A verilog_type=reg}
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C {lab_pin.sym} 160 -280 0 0 {name=p49 lab=ADD_A[4:0] verilog_type=reg}
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C {lab_pin.sym} 160 -320 0 0 {name=p50 lab=DIN_A[7:0] verilog_type=reg}
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C {lab_pin.sym} 160 -240 0 0 {name=p51 lab=WEN_A verilog_type=reg}
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C {lab_pin.sym} 160 -220 0 0 {name=p52 lab=OEN_A verilog_type=reg}
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C {lab_pin.sym} 160 -200 0 0 {name=p53 lab=CK_A verilog_type=reg}
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C {lab_pin.sym} 160 -260 0 0 {name=p54 lab=CEN_A verilog_type=reg}
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C {lab_pin.sym} 160 -300 0 0 {name=p55 lab=M_A[7:0] verilog_type=reg}
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C {adc_bridge.sym} 190 -390 0 0 {name=v1 delay=1}
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C {adc_bridge.sym} 190 -350 0 0 {name=v2 delay=1}
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C {adc_bridge.sym} 190 -320 0 0 {name=v3 delay=1}
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C {adc_bridge.sym} 190 -300 0 0 {name=v4 delay=1}
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C {adc_bridge.sym} 190 -280 0 0 {name=v5 delay=1}
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C {adc_bridge.sym} 190 -260 0 0 {name=v6 delay=1}
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C {adc_bridge.sym} 190 -240 0 0 {name=v7 delay=1}
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C {adc_bridge.sym} 190 -220 0 0 {name=v8 delay=1}
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C {adc_bridge.sym} 190 -200 0 0 {name=v9 delay=1}
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