106 lines
2.6 KiB
XML
106 lines
2.6 KiB
XML
v {xschem version=2.9.6 file_version=1.1}
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G {}
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V {
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integer tck = 10000; // 10 ns
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task cycle;
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input [7:0] add;
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input cen;
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input oen;
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input wen;
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input [15:0] din;
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begin
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CEN = cen;
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OEN = oen;
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WEN = wen;
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ADD = add;
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if(wen == 0) DIN = din;
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else DIN = 16'hxxxx;
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#(tck/4);
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CK=1;
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#(tck/2);
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CK=0;
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#(tck/4);
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end endtask
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initial begin
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$dumpfile("dumpfile.vcd");
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$dumpvars;
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CK = 0;
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WEN = 1;
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OEN = 1;
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CEN = 1;
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ADD = 8'h00;
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DIN = 16'h 0000;
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M = 16'h0000;
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//// read cycles
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// add cen oen wen din
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cycle('h00, 0, 0, 1, 16'h0000);
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cycle('h01, 0, 0, 1, 16'h0000);
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cycle('h02, 0, 0, 1, 16'h0000);
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///// write cycle
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// add cen oen wen din
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cycle('h01, 0, 1, 0, 16'h4444);
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//// read cycles
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// add cen oen wen din
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cycle('h00, 0, 0, 1, 16'h0000);
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cycle('h01, 0, 0, 1, 16'h0000);
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cycle('h02, 0, 0, 1, 16'h0000);
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$finish;
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end
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}
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S {}
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E {}
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B 0 40 -940 1260 -270 {}
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B 19 40 -940 1260 -270 {}
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T {parameters:
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dim: number of address bits
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width: number of data bits
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hex: -1 -> do not preset memory with datafile
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0 -> preset memory with binary datafile
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1 -> preset memory with hex datafile
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datafile: name of memory initialization file
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access_delay: from clock rising edge to internal data ready
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oe_delay: output buffer delay (OEN low to DOUT ready)
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modulename: a string that is printed during simulation
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total access time from clock positive edge is access_delay + oe_delay
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Memory initialization file contains just one word per line (start from address 0)
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HEX BINARY
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----------------------------
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1234 0001001000110100
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abcd 1010101111001101
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ffaa 1111111110101010
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.... ................
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.... ................
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} 70 -920 0 0 0.4 0.4 {font=monospace}
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T {Verilog example of parametric memory module} 50 -1020 0 0 1 1 {}
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C {ram.sym} 740 -160 0 0 {name=x1
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dim=8
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width=16
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hex=1
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datafile=ram.list
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modulename=ram
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access_delay=3000
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oe_delay=300}
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C {lab_pin.sym} 890 -220 0 1 {name=p1 lab=DOUT[15:0]}
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C {verilog_timescale.sym} 40 -137.5 0 0 {name=s1 timestep="1ps" precision="1ps" }
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C {lab_pin.sym} 590 -220 0 0 {name=p9 lab=ADD[7:0] verilog_type=reg}
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C {lab_pin.sym} 590 -180 0 0 {name=p10 lab=DIN[15:0] verilog_type=reg}
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C {lab_pin.sym} 590 -160 0 0 {name=p11 lab=WEN verilog_type=reg}
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C {lab_pin.sym} 590 -120 0 0 {name=p12 lab=OEN verilog_type=reg}
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C {lab_pin.sym} 590 -100 0 0 {name=p13 lab=CK verilog_type=reg}
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C {lab_pin.sym} 590 -140 0 0 {name=p14 lab=CEN verilog_type=reg}
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C {lab_pin.sym} 590 -200 0 0 {name=p15 lab=M[15:0] verilog_type=reg}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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