75 lines
3.0 KiB
XML
75 lines
3.0 KiB
XML
v {xschem version=2.9.5_RC8 file_version=1.1}
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G {}
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V {}
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S {}
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E {}
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N 350 -280 350 -260 {lab=#net1}
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N 450 -280 610 -280 {lab=#net1}
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N 310 -280 310 -230 {lab=B}
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N 90 -280 310 -280 {lab=B}
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N 350 -200 350 -160 {lab=#net2}
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N 210 -390 210 -370 {lab=#net1}
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N 210 -370 350 -370 {lab=#net1}
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N 170 -130 310 -130 {lab=A}
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N 170 -330 170 -130 {lab=A}
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N 90 -330 170 -330 {lab=A}
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N 310 -420 310 -280 {lab=B}
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N 350 -390 350 -370 {lab=#net1}
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N 170 -420 170 -330 {lab=A}
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N 530 -330 530 -270 {lab=Z}
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N 660 -330 700 -330 {lab=Z}
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N 590 -210 660 -210 {lab=#net3}
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N 590 -210 590 -160 {lab=#net3}
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N 660 -330 660 -270 {lab=Z}
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N 530 -330 660 -330 {lab=Z}
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N 530 -210 590 -210 {lab=#net3}
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N 610 -360 610 -280 {lab=#net1}
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N 450 -130 550 -130 {lab=#net1}
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N 450 -280 450 -130 {lab=#net1}
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N 210 -420 220 -420 {lab=VDD}
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N 350 -420 360 -420 {lab=VDD}
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N 530 -420 540 -420 {lab=VDD}
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N 530 -360 540 -360 {lab=VDD}
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N 650 -360 660 -360 {lab=VDD}
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N 350 -130 360 -130 {lab=GND}
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N 350 -230 360 -230 {lab=GND}
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N 530 -240 540 -240 {lab=GND}
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N 660 -240 670 -240 {lab=GND}
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N 590 -130 600 -130 {lab=GND}
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N 350 -280 450 -280 {lab=#net1}
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N 350 -370 350 -280 {lab=#net1}
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C {ipin.sym} 90 -280 0 0 {name=g1 lab=B}
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C {opin.sym} 700 -330 0 0 {name=g2 lab=Z verilog_type=wire}
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C {gnd.sym} 350 -100 0 0 {name=lg1 lab=GND}
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C {vdd.sym} 350 -450 0 0 {name=lg2 lab=VDD}
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C {vdd.sym} 210 -450 0 0 {name=lg3 lab=VDD}
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C {gnd.sym} 590 -100 0 0 {name=l2 lab=GND}
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C {vdd.sym} 650 -390 0 0 {name=l1 lab=VDD}
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C {vdd.sym} 530 -450 0 0 {name=l6 lab=VDD}
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C {lab_pin.sym} 490 -420 0 0 {name=l4 lab=A}
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C {lab_pin.sym} 490 -360 0 0 {name=l7 lab=B}
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C {lab_pin.sym} 490 -240 0 0 {name=l3 lab=B}
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C {lab_pin.sym} 620 -240 0 0 {name=l8 lab=A}
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C {nmos4.sym} 330 -130 0 0 {name=M1 model=nmos w=10u l=1u m=1}
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C {nmos4.sym} 570 -130 0 0 {name=M2 model=nmos w=10u l=1u m=1}
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C {nmos4.sym} 640 -240 0 0 {name=M3 model=nmos w=10u l=1u m=1}
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C {nmos4.sym} 510 -240 0 0 {name=M4 model=nmos w=10u l=1u m=1}
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C {nmos4.sym} 330 -230 0 0 {name=M5 model=nmos w=10u l=1u m=1}
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C {pmos4.sym} 190 -420 0 0 {name=M6 model=pmos w=10u l=1u m=1}
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C {pmos4.sym} 330 -420 0 0 {name=M7 model=pmos w=10u l=1u m=1}
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C {pmos4.sym} 510 -420 0 0 {name=M8 model=pmos w=10u l=1u m=1}
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C {pmos4.sym} 510 -360 0 0 {name=M9 model=pmos w=10u l=1u m=1}
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C {pmos4.sym} 630 -360 0 0 {name=M10 model=pmos w=10u l=1u m=1}
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C {lab_pin.sym} 220 -420 0 1 {name=l5 sig_type=std_logic lab=VDD}
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C {lab_pin.sym} 360 -420 0 1 {name=l9 sig_type=std_logic lab=VDD}
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C {lab_pin.sym} 540 -420 0 1 {name=l10 sig_type=std_logic lab=VDD}
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C {lab_pin.sym} 540 -360 0 1 {name=l11 sig_type=std_logic lab=VDD}
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C {lab_pin.sym} 660 -360 0 1 {name=l12 sig_type=std_logic lab=VDD}
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C {lab_pin.sym} 360 -130 0 1 {name=l13 sig_type=std_logic lab=GND}
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C {lab_pin.sym} 360 -230 0 1 {name=l14 sig_type=std_logic lab=GND}
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C {lab_pin.sym} 540 -240 0 1 {name=l15 sig_type=std_logic lab=GND}
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C {lab_pin.sym} 670 -240 0 1 {name=l16 sig_type=std_logic lab=GND}
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C {lab_pin.sym} 600 -130 0 1 {name=l17 sig_type=std_logic lab=GND}
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C {title.sym} 160 -30 0 0 {name=l18 author="Stefan Schippers"}
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C {ipin.sym} 90 -330 0 0 {name=g0 lab=A}
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