18 lines
491 B
Plaintext
18 lines
491 B
Plaintext
v {xschem version=2.9.5_RC5 file_version=1.1}
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G {type=delay
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verilog_ignore=true
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vhdl_ignore=true
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format="@name [ @@s ] [ @@d ] @adc_bridge_model"
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template="name=A1 adc_bridge_model= adc_buff"
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}
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V {}
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S {}
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E {}
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L 4 -30 0 30 0 {}
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L 4 -10 -5 10 0 {}
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L 4 -10 5 10 0 {}
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B 5 27.5 -2.5 32.5 2.5 {name=d dir=out verilog_type=wire propagate_to=1}
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B 5 -32.5 -2.5 -27.5 2.5 {name=s dir=in verilog_type=wire propagate_to=0}
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T {@name} -25 -10 0 0 0.12 0.12 {}
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T {@adc_bridge_model} 0 -10 0 0 0.12 0.12 {}
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