184 lines
7.8 KiB
HTML
184 lines
7.8 KiB
HTML
<!DOCTYPE html>
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<html>
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<head>
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<title>SIMULATION</title>
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<link rel="stylesheet" type="text/css" href="xschem_man.css" />
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<style type="text/css">
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/* Local styling goes here */
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p{padding: 15px 30px 10px;}
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</style>
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</head>
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<body>
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<!-- start of slide -->
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<div class="content">
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<!-- navigation buttons -->
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<a href="net_probes.html" class="prev">PREV</a>
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<!-- slide title -->
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<h1>SIMULATION</h1><br>
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<p>
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One of the design goals of XSCHEM is the ability to launch a simulation without additional manual file editing.
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For this purpose XSCHEM stores in a schematic not only the circuit but also the simulator
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settings and the additional files that are needed.
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For example there is a <kbd>devices/netlist.sym</kbd> and <kbd>devices/netlist_not_shown.sym</kbd> symbol that
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can be placed in a schematic acting as a container of text files for all the needed SPICE models and any
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additional information to make the schematic ready for simulation.
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</p>
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<img src="simulation10.png">
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<p>
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The <kbd>devices/netlist_not_shown</kbd> symbol shown in the picture (with name MODELS) for example contains
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all the spice models of the components used in the schematic, this makes
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the schematic self contained, no additional files are needed to run a simulation.
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After generating the netlist (for example poweramp.spice) the resulting SPICE netlist can be sent directly for
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simulation (for example <kbd>hspice -i poweramp.spice</kbd> for the Hspice(TM) simulator).
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</p>
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<h3> VERILOG SIMULATION</h3>
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<p> This is a tutorial showing how to run a simulation with XSCHEM. The first important thing to
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note is that XSCHEM is just a schematic editor, so we need to setup valid bindings to
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simulators. For this tutorial we plan to do a <kbd>Verilog</kbd>
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simulation since there is a very good open source simulator available, called
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<a href="http://iverilog.icarus.com">Icarus Verilog</a>.
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There is also a good waveform viewer called
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<a href="https://sourceforge.net/projects/gtkwave">gtkwave</a>
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that is able to show simulator results. Install these two valuable tools and setup
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simulator invocation by using the Simulator configurator (<kbd>Simulation->Configure Simulators and tools</kbd>).
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</p>
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<img src="simulation11.png">
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<p>
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The text entry on the verilog line is the command to invoke icarus verilog simulation. <kbd>$N</kbd>
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will be expanded to the netlist file (<kbd>$netlist_dir/greycnt.v</kbd>), while <kbd>$n</kbd>
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will be replaced with the circuit name without extension (<kbd>$netlist_dir/greycnt</kbd>).
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Note also the command to invoke gtkwave on the vcd file generated by theverilog simulation.
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If <kbd>Save Configuration</kbd> button is pressed the changes are made permanent by saving
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in a <kbd>~/.xschem/simrc</kbd> file.
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</p>
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<p>
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In the XSCHEM distribution there is one example design, <kbd>examples/greycnt.sch</kbd>.<br>
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Load this design:
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</p>
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<pre class="code">
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user:~$ xschem examples/greycnt
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</pre>
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<img src="simulation1.png">
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<p>
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This testbench has a 8 bit input vector A[7:0] and two output vectors, B[7:0] and C[7:0].
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B[7:0] is a grey coded vector, this mean that if A[7:0] is incremented as a binary number
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B[7:0] will increment by changing only one bit at a time. The C[7:0] vector is the reverse transformation
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from grey-code to binary, so at the end if simulation goes well C[7:0] == A[7:0].
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In this schematic there are some components, the first one is the <kbd>xnor</kbd> gate, the second one is
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the <kbd>assign</kbd> element. The 'xnor' performs the logical 'Not-Xor' of its inputs, while 'assign'
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just propagates the input unchanged to the output, optionally with some delay.
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This is useful if we want to change the name of a net
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(putting two labels with different names on the same net is not allowed, since this is normally an error,
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leading to a short circuit).
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</p>
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<p>
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An Ex-Nor gate can be represented as a verilog primitive, so for the xnor gate we just need to setup
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a <kbd>verilog_format</kbd> attribute in the global property string of the <kbd>xnor.sym</kbd> gate:
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</p>
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<img src="simulation2.png">
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<p>
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the 'assign' symbol is much simpler, in this property string you see the definition for SPICE
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(<kbd>format</kbd> attribute), Verilog (<kbd>verilog_format</kbd>) and VHDL (<kbd>vhdl_format</kbd>).
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This shows how a single symbol can be used for different netlist formats.
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</p>
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<img src="simulation3.png">
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<p>
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While showing the top-level testbench <kbd>greycnt</kbd> set XSCHEM in Verilog mode
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(menu <kbd>Options->Verilog</kbd> radio button, or <kbd><Shift>V</kbd> key) and press
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the edit property <kbd>'q'</kbd> key, you will see some verilog code:
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</p>
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<img src="simulation4.png">
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<p>
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This is the testbench behavioral code that generates stimuli for the simulation and gives
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instructions on where to save simulation results. If you generate the verilog netlist with
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the <kbd>Netlist</kbd> button on the right side of the menu bar (or <kbd><Shift>N</kbd>
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key) a <kbd>greycnt.v</kbd> file will be generated in the simulation directory
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(<kbd>${HOME}/xschem_library/simulations</kbd> is the default path in the XSCHEM distribution, but
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can be changed with the <kbd>set netlist_dir $env(HOME)/simulations</kbd> in <kbd>xschemrc</kbd> file):
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</p>
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<pre class="code">
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`timescale 1ps/1ps
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module greycnt (
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output wire [7:0] B,
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output wire [7:0] C
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);
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reg [7:0] A ;
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xnor #(1 , 1 ) x2 ( B[4] , A[5] , A[4] );
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xnor #(1 , 1 ) x3 ( B[5] , A[6] , A[5] );
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xnor #(1 , 1 ) x14 ( B[6] , A[7] , A[6] );
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assign #1 B[7] = A[7] ;
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xnor #(1 , 1 ) x1 ( B[1] , A[2] , A[1] );
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xnor #(1 , 1 ) x4 ( B[2] , A[3] , A[2] );
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xnor #(1 , 1 ) x5 ( B[3] , A[4] , A[3] );
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xnor #(1 , 1 ) x6 ( B[0] , A[1] , A[0] );
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xnor #(1 , 1 ) x7 ( C[4] , C[5] , B[4] );
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xnor #(1 , 1 ) x8 ( C[5] , C[6] , B[5] );
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xnor #(1 , 1 ) x9 ( C[6] , C[7] , B[6] );
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assign #1 C[7] = B[7] ;
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xnor #(1 , 1 ) x10 ( C[1] , C[2] , B[1] );
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xnor #(1 , 1 ) x11 ( C[2] , C[3] , B[2] );
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xnor #(1 , 1 ) x12 ( C[3] , C[4] , B[3] );
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xnor #(1 , 1 ) x13 ( C[0] , C[1] , B[0] );
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initial begin
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$dumpfile("dumpfile.vcd");
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$dumpvars;
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A=0;
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end
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always begin
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#1000;
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$display("%08b %08b", A, B);
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A=A + 1;
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if(A==0) $finish;
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end
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endmodule
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</pre>
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<p>
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you will recognize the behavioral code right after the netlist specifying the connection of
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nets to the xnor and assign gates and all the necessary verilog declarations.
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If you press the <kbd>Simulation</kbd> button the <kbd>Icarus Verilog</kbd> simulator will be executed
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to compile (iverilog) and run (vvp) the simulation, a terminal window will show the simulation output,
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in this case the input vector A[7:0] and the grey coded B[7:0] vectors are shown. You can quit the
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simulator log window by pressing <kbd>'q'</kbd>.
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</p>
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<img src="simulation5.png">
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<p>
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If simulation completes with no errors waveforms can be viewed. Press the <kbd>Waves</kbd> button
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in the top-right of the menu bar, you may add waveforms in the gtkwave window:
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</p>
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<img src="simulation6.png">
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<p>
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If the schematic contains errors that the simulator can not handle instead of the simulation
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log a window showing the error messages from the simulator is shown:
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</p>
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<img src="simulation7.png">
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<p>
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To facilitate the debug you may wish to edit the netlist (<kbd>Simulation->Edit Netlist</kbd>)
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to locate the error, in the picture below i inserted deliberately a random string to
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trigger the failure:
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</p>
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<img src="simulation8.png">
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<p>
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As you can see the error is in the behavioral code of the top level greycnt schematic, so edit the
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global property (<kbd>'q'</kbd> key with no component selected) and fix the error.
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</p>
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<img src="simulation9.png">
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<!-- end of slide -->
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<div class="filler"></div>
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</div>
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