39 lines
1.4 KiB
XML
39 lines
1.4 KiB
XML
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2023 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 260 -300 290 -300 { lab=A}
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N 260 -300 260 -200 { lab=A}
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N 260 -200 290 -200 { lab=A}
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N 370 -300 400 -300 { lab=Y}
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N 400 -300 400 -200 { lab=Y}
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N 370 -200 400 -200 { lab=Y}
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N 220 -250 260 -250 { lab=A}
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C {ipin.sym} 220 -250 0 0 {name=p1 lab=A}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {inv_ngspice.sym} 330 -200 0 0 {name=x1}
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C {inv_ngspice.sym} 330 -300 0 1 {name=x2 RUP=300k RDOWN=200k}
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C {lab_pin.sym} 400 -250 0 1 {name=l2 sig_type=std_logic lab=Y}
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