63 lines
1.9 KiB
XML
63 lines
1.9 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2023 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {
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process(CK, RESET) begin
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if RESET = '1' then
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D <= (others => '0');
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elsif CK'event and CK = '1' and LOAD = '1' then
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D <= DATA_IN;
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end if;
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end process;
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DATA_OUT <= D after delay;
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}
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V {reg [width-1:0] D;
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always @(posedge CK or posedge RESET) begin
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if(RESET) begin
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D <= 0;
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end
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else begin
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if(LOAD) begin
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D <= DATA_IN;
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end
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end
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end
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assign #del DATA_OUT=D;
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}
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S {}
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E {}
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C {opin.sym} 440 -230 0 0 {name=p3 lab=DATA_OUT[width-1:0] verilog_type=wire}
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C {ipin.sym} 280 -210 0 0 {name=p2 lab=CK}
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C {ipin.sym} 280 -190 0 0 {name=p4 lab=RESET}
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C {ipin.sym} 280 -250 0 0 {name=p7 lab=DATA_IN[width-1:0]}
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C {ipin.sym} 280 -230 0 0 {name=p1 lab=LOAD}
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C {verilog_timescale.sym} 360 -577.5 0 0 {name=s1 timestep="1ps" precision="1ps" }
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C {title.sym} 160 -30 0 0 {name=l2}
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C {arch_declarations.sym} 360 -350 0 0 { signal d : std_logic_vector(width-1 downto 0);
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}
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C {use.sym} 360 -460 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;}
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