39 lines
1.4 KiB
Plaintext
39 lines
1.4 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2023 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=logo
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template="name=l1 author=\\"Stefan Schippers\\""
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verilog_ignore=true
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vhdl_ignore=true
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spice_ignore=true
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tedax_ignore=true}
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V {}
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S {}
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E {}
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L 6 225 0 1020 0 {}
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L 6 -160 0 -95 0 {}
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P 5 13 5 -30 -25 0 5 30 -15 30 -35 10 -55 30 -75 30 -45 0 -75 -30 -55 -30 -35 -10 -15 -30 5 -30 {fill=true}
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T {@path @schname_ext} 235 5 0 0 0.4 0.4 {}
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T {@author} 235 -25 0 0 0.4 0.4 {}
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T {@time_last_modified} 1020 -25 0 1 0.4 0.3 {}
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T {SCHEM} 5 -25 0 0 1 1 {}
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