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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 973d01f3bb update Changelog to 3.4.5 2024-05-28 16:46:26 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin drc_check(): if no fet_drc procedure found do nothing 2024-04-25 09:13:23 +02:00
doc update docs on new `xschem cursor` and `xschem swap_cursors` commands 2024-05-22 00:08:15 +02:00
scconfig add missing scconfig/src/tty/ dir 2024-05-02 10:33:10 +02:00
src Use by default *.{sym,tcl} pattern in insert symbol and component browser 2024-05-28 14:32:20 +02:00
tests tests/netlisting.tcl: better error checking. Distinguish a general failure from an ERC netlist error (xschem return code 10) 2024-05-17 00:48:47 +02:00
xschem_library if top level schematic has an associated symbol (.sym) file ensure their ports match, otherwise issue an error. if netlisting fails return non zero exit code if netlisting from command line 2024-05-09 02:10:45 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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Makefile.conf.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions