365 lines
9.2 KiB
Awk
Executable File
365 lines
9.2 KiB
Awk
Executable File
#!/usr/bin/awk -f
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#
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# File: make_sym.awk
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#
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# This file is part of XSCHEM,
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# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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# simulation.
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# Copyright (C) 1998-2024 Stefan Frederik Schippers
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#
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BEGIN{
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if( ARGV[1] ~ /^[1-9][0-9]*$/ ) {
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width=ARGV[1]+0
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ARGV[1]=""
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} else {
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width=150
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}
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}
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FNR == 1 {
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if (_filename_ != "") endfile(_filename_)
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_filename_ = FILENAME
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beginfile(FILENAME)
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}
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END { endfile(_filename_) }
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function beginfile(f)
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{
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sym=name=f
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sub(/^.*\//,"",name)
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name_ext=name
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sub(/\.sch.*$/,"",name)
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sub(/\.sch.*$/,".sym",sym)
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print "**** symbol-izing: " sym " ****"
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template="" ; start=0
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while((getline symline <sym) >0) {
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if(symline ~ /^[K] \{/ ) start=1
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if(start) template=template symline "\n"
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if(symline ~ /\} *$/) start=0
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}
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close(sym)
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size=2.5
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space=20
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lwidth=20
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textdist=5
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labsize=0.2
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titlesize=0.3
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text_voffset=20
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lab_voffset=4
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ip=op=n_pin=0
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print "v {xschem version=3.4.8RC file_version=1.3}" > sym
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if(template !~/^{[ \t\n]*$/) {
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printf "%s", "K {type=subcircuit\nformat=\"@name @pinlist @symname\"\n" >sym
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printf "%s\n", "template=\"name=x1\"" >sym
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printf "%s", "}\n" >sym
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}
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else print template >sym
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print "T {@symname}" ,-length(name_ext)/2*titlesize*30, -text_voffset*titlesize,0,0,
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titlesize, titlesize, "{}" >sym
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}
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/^C \{.*generic_pin(\.sym)?\}/{
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get_end_line()
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process_line()
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type_pin[n_pin]=generic_type
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dir_pin[n_pin]="generic"
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y_pin[n_pin] = $4+0 # y coordinate of pin 20140519
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index_pin[n_pin] = n_pin # one level indirection for sorting pins 20140519
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value_pin[n_pin]=value
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label_pin[n_pin] = pin_label
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props_pin[n_pin] = rest_of_props()
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n_pin++
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ip++
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}
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/^C \{.*ipin(\.sym)?\}/{
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get_end_line()
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process_line()
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type_pin[n_pin]=sig_type
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verilog_pin[n_pin]=verilog_type
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dir_pin[n_pin]="ipin"
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y_pin[n_pin] = $4+0 # y coordinate of pin 20140519
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index_pin[n_pin] = n_pin # one level indirection 20140519
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value_pin[n_pin]=value
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label_pin[n_pin] = pin_label
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props_pin[n_pin] = rest_of_props()
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n_pin++
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ip++
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}
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$0 ~ /^C \{.*opin(\.sym)?\}/ && $0 !~ /^C \{.*iopin(\.sym)?\}/ {
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get_end_line()
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process_line()
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type_pin[n_pin]=sig_type
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verilog_pin[n_pin]=verilog_type
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dir_pin[n_pin]="opin"
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y_pin[n_pin] = $4+0 # y coordinate of pin 20140519
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index_pin[n_pin] = n_pin # one level indirection 20140519
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value_pin[n_pin]=value
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label_pin[n_pin] = pin_label
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props_pin[n_pin] = rest_of_props()
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n_pin++
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op++
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}
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/^C \{.*iopin(\.sym)?\}/{
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print "iopin"
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get_end_line()
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process_line()
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type_pin[n_pin]=sig_type
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verilog_pin[n_pin]=verilog_type
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dir_pin[n_pin]="iopin"
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y_pin[n_pin] = $4+0 # y coordinate of pin 20140519
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index_pin[n_pin] = n_pin # one level indirection 20140519
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value_pin[n_pin]=value
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label_pin[n_pin] = pin_label
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props_pin[n_pin] = rest_of_props()
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n_pin++
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op++
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}
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function rest_of_props()
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{
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sub(/^C \{[^}]+\}.*\{/,"")
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sub(/\}[ \t]*$/, "")
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sub(/verilog_type[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
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sub(/sig_type[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
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sub(/lab[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
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sub(/value[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
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sub(/name[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
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sub(/^[ \t]*/, " ") # always begin with a space separator
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sub(/[ \t]*$/, "") # remove trailing white space
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sub(/^[ \t]*$/, "")
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return $0
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}
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function process_line()
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{
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print "process_line"
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sig_type="" #20070726 # "std_logic"
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verilog_type= "" # 20070726 "wire" #09112003
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pin_label=""
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value=""
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generic_type=""
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if($0 ~ /^.*lab=/)
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{
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pin_label=$0
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sub(/^.*lab=/,"",pin_label)
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sub(/[ }].*$/,"",pin_label)
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}
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if($0 ~ /^.*verilog_type=/) #09112003
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{
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verilog_type=$0
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sub(/^.*verilog_type=/,"",verilog_type)
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sub(/[}].*$/,"",verilog_type)
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sub(/ $/,"",verilog_type)
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}
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if($0 ~ /^.*sig_type=/)
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{
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sig_type=$0
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sub(/^.*sig_type=/,"",sig_type)
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sub(/[ }].*$/,"",sig_type)
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}
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if($0 ~ /^.*generic_type=/)
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{
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generic_type=$0
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sub(/^.*generic_type=/,"",generic_type)
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sub(/[}].*$/,"",generic_type)
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sub(/[a-zA-Z0-9]+=.*$/,"",generic_type) #03062002, allow spaces
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print "------------------------" $0 "-->" generic_type
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}
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if($0 ~ /^.*value=/)
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{
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value=$0
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if(value ~ /value="/)
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{
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sub(/^.*value="/,"",value)
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value= "\"" substr(value,1, match(value, /[^\\]"/) ) "\""
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}
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else
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{
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sub(/^.*value=/,"",value)
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sub(/[ }].*$/,"",value)
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}
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}
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# print "process_line: returning:" $0
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# print "process_line: pin_label=" pin_label " verilog_type=" verilog_type
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}
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## join lines like this:
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## C {ipin.sym} ........ {lab=xxx
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## verilog_type=reg}
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function get_end_line()
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{
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print "get_end_line"
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while($0 !~ /\}[ \t]*$/) {
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a=$0
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getline
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$0 = a " " $0
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}
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}
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function endfile(f) {
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n=ip;if(op>n) n=op
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if(n==0) n=1
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m=(n-1)/2
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y=-m*space
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x=-width
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print "T {@name}",-x-lwidth+5, y-space/2-8-lab_voffset,0,0,labsize, labsize,"{}" >sym
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print "P 4 5", \
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(-x-lwidth) ,y-space/2, \
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(x+lwidth) , y-space/2, \
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(x+lwidth), y+n*space-space/2, \
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(-x-lwidth), y+n*space-space/2, \
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(-x-lwidth) ,y-space/2, \
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"{}" > sym
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hsort_key(index_pin, y_pin, n_pin) # 20140519
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num_i = num_o = 0 #20140519
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for(ii=0;ii<n_pin;ii++)
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{
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i = index_pin[ii] # 20140519
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dir=dir_pin[i]
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value=value_pin[i]
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sig_type=type_pin[i]
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verilog_type=verilog_pin[i]
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vert = verilog_type ? (" verilog_type=" verilog_type) : ""
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vhdt = sig_type ? (" sig_type=" sig_type) : ""
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if(dir=="generic")
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{
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printf "B 3 " (x-size) " " (y+num_i*space-size) " " (x+size) " " (y+num_i*space+size) \
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" {name=" label_pin[i] " generic_type=" sig_type >sym
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if(value !="") printf " value=" value >sym
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printf props_pin[i] > sym
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printf "}\n" >sym
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print "L 4 " x,y+num_i*space,x+lwidth, y+num_i*space,"{}" >sym
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print "T {" label_pin[i] "}",x+lwidth+textdist,y+num_i*space-lab_voffset,0,0,labsize, labsize, "{}" >sym
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num_i++ # 20140519
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}
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if(dir=="ipin")
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{
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printf "B 5 " (x-size) " " (y+num_i*space-size) " " (x+size) " " (y+num_i*space+size) \
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" {name=" label_pin[i] vhdt vert " dir=in" >sym
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if(value !="") printf " value=" value >sym
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printf props_pin[i] > sym
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printf "}\n" >sym
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print "L 4 " x,y+num_i*space,x+lwidth, y+num_i*space,"{}" >sym
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print "T {" label_pin[i] "}",x+lwidth+textdist,y+num_i*space-lab_voffset,0,0,labsize, labsize, "{}" >sym
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num_i++ # 20140519
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}
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if(dir=="opin")
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{
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printf "B 5 " (-x-size) " " (y+num_o*space-size) " " (-x+size) " " (y+num_o*space+size) \
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" {name=" label_pin[i] vhdt vert " dir=out" >sym
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if(value !="") printf " value=" value >sym
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printf props_pin[i] > sym
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printf "}\n" >sym
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print "L 4 " (-x-lwidth),(y+num_o*space),-x, (y+num_o*space),"{}" >sym
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print "T {" label_pin[i] "}",-x-lwidth-textdist,y+num_o*space-lab_voffset,0,1,labsize, labsize, "{}" >sym
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num_o++ # 20140519
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}
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if(dir=="iopin")
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{
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printf "B 5 " (-x-size) " " (y+num_o*space-size) " " (-x+size) " " (y+num_o*space+size) \
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" {name=" label_pin[i] vhdt vert " dir=inout" >sym
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if(value !="") printf " value=" value >sym
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printf props_pin[i] > sym
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printf "}\n" >sym
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print "L 7 " (-x-lwidth),(y+num_o*space),-x, (y+num_o*space),"{}" >sym
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print "T {" label_pin[i] "}",-x-lwidth-textdist,y+num_o*space-lab_voffset,0,1,labsize, labsize, "{}" >sym
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num_o++ # 20140519
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}
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}
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close(sym)
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}
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## sort array[0...n-1] based on keys ra[0...n-1]
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function hsort_key(array, ra, n, i, j, c, root, temp)
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{
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for (i = 1; i < n; i++)
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{
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c = i
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do
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{
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root = int((c - 1) / 2)
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if (comp(ra[root], ra[c])) # to create MAX ra array
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{
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temp = ra[root]
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ra[root] = ra[c]
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ra[c] = temp
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temp = array[root]
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array[root] = array[c]
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array[c] = temp
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}
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c = root
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} while (c != 0)
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}
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for (j = n - 1; j >= 0; j--)
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{
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temp = ra[0]
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ra[0] = ra[j] # swap max element with rightmost leaf element
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ra[j] = temp
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temp = array[0]
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array[0] = array[j]
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array[j] = temp
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root = 0
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do
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{
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c = 2 * root + 1 # left node of root element
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if (comp(ra[c], ra[c + 1]) && c < j-1)
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c++
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if (comp(ra[root], ra[c]) && c<j) # again rearrange to max ra array
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{
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temp = ra[root]
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ra[root] = ra[c]
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ra[c] = temp
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temp = array[root]
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array[root] = array[c]
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array[c] = temp
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}
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root = c
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} while (c < j)
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}
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}
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function comp(a,b)
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{
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return a<b
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}
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