141 lines
4.3 KiB
Tcl
141 lines
4.3 KiB
Tcl
#
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# File: hspice_backannotate.tcl
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#
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# This file is part of XSCHEM,
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# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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# simulation.
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# Copyright (C) 1998-2023 Stefan Frederik Schippers
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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proc read_hspice_log {f} {
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global current_probe voltage
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set fd [open $f]
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while {[gets $fd line] >= 0} {
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regsub -all {\r} $line {} line
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regsub {^ *\+} $line { + } line
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if [regexp {\*\*\*\*\*\*.*operating point information} $line] {
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set vnodes 1
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}
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if [regexp {\*\*\*\*.*voltage sources} $line] {
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set vnodes 0
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set vsources 1
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}
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if [regexp {total voltage source power} $line] {
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set vsources 0
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}
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if { [lindex $line 0] == {element} && $vsources } {
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set vsource_name $line
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}
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if { [lindex $line 0] == {current} && $vsources } {
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for {set i 1} {$i < [llength $line]} { incr i } {
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set vsource [lindex $vsource_name $i]
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set current [lindex $line $i]
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if {[regexp {^0:} $vsource]} {
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if {[regsub {^.*:} $vsource {} vsource]} {
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set current_probe($vsource) $current
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puts "$vsource --> $current"
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}
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}
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}
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}
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if { [lindex $line 0] == {+} && $vnodes} {
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regsub -all {=} $line { = } line
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for { set i 1} {$i < [llength $line]} { set i [expr $i+3]} {
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set node [lindex $line $i]
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set volt [lindex $line [expr $i+2]]
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if {[regsub {^0:} $node {} node]} {
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set voltage($node) $volt
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puts "$node --> $volt"
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}
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}
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}
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}
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close $fd
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}
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proc get_voltage { n } {
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global voltage
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if { abs($voltage([string tolower $n])) < 1e-3 } {
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return [format %.4e $voltage([string tolower $n])]
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} else {
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return [format %.4g $voltage([string tolower $n])]
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}
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# return DELETE
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}
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proc get_diff_voltage { p m } {
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global voltage
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return [format %.4e [expr $voltage([string tolower $p]) - $voltage([string tolower $m]) ] ]
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# return DELETE
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}
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proc get_current { n } {
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global current_probe
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if {abs($current_probe([string tolower $n])) <1e-3} {
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return [format %.4e $current_probe([string tolower $n])]
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} else {
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return [format %.4g $current_probe([string tolower $n])]
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}
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# return DELETE
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}
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proc annotate {} {
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### disable screen redraw and undo when looping to speed up performance
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### but save state on undo stack before doing backannotations.
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xschem push_undo
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xschem set no_undo 1
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xschem set no_draw 1
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read_hspice_log $::netlist_dir/hspice.out
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set lastinst [xschem get instances]
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for { set i 0 } { $i < $lastinst } {incr i } {
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set name [xschem getprop instance $i name]
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set type [xschem getprop instance $i cell::type]
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if { $type == "probe"} {
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set net [xschem instance_net $i p]
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if {[catch {xschem setprop instance $i voltage [get_voltage $net] fast} err]} {
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puts "1 error : $err net: $net"
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}
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}
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if { $type == "current_probe"} {
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if {[catch {xschem setprop instance $i current [get_current $name] fast} err]} {
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puts "2 error : $err"
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}
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}
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if { $type == "differential_probe"} {
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set netp [xschem instance_net $i p]
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set netm [xschem instance_net $i m]
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if {[catch {xschem setprop instance $i voltage [get_diff_voltage $netp $netm] fast} err]} {
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puts "3 error : $err"
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}
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}
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# puts "$i $name $type"
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}
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# re-enable undo and draw
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xschem set no_undo 0
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xschem set no_draw 0
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xschem redraw
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### xschem setprop instructions have not altered circuit topology so
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### in this case a connectivity rebuild is not needed.
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# xschem rebuild_connectivity
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#
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#
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}
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