71 lines
1.5 KiB
Awk
Executable File
71 lines
1.5 KiB
Awk
Executable File
#!/usr/bin/awk -f
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#
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# File: convert_to_verilog2001.awk
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#
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# This file is part of XSCHEM,
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# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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# simulation.
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# Copyright (C) 1998-2021 Stefan Frederik Schippers
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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NF==3 && $0 ~/^module/ {
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module=1
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port_decl=0
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parameter = ""
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comma=0
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print
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next
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}
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module==1 && $0 == ");" {
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port_decl=1
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module=0
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next
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}
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port_decl==1 && $1 ~ /^(output|input|inout)$/{
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dir=$1 #20161118
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getline
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sub(/;[ \t]*$/,"")
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$1 = dir " " $1
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if(comma) printf ",\n"
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printf " %s", $0
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comma=1
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next
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}
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port_decl==1 && $0 ~ /^parameter/{
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if(parameter!="") parameter = parameter "\n"
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parameter = parameter $0
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next
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}
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port_decl==1 && $0 ~/^[ \t]*$/{
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port_decl=0
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printf "\n);\n"
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print parameter
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next
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}
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module==1 || port_decl==1{
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next
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}
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{
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print
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}
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