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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 4e8e4cea20 poweramp.sch fixes in sim commands 2021-07-13 18:37:01 +02:00
XSchemWin make_sym_lcc.awk: declare "value" as local variable inside process_box_line() to avoid clashes with global "value" 2021-06-05 08:58:38 +02:00
doc removed/updated obsolete keybinding descriptions, removed status check on Delete key events 2021-01-13 13:44:57 +01:00
scconfig poweramp.sch fixes in sim commands 2021-07-13 18:37:01 +02:00
src Talk To Gaw (ttg) improvement: use "sel" instead of "p0" for panel selection, meaning "selected panel (or 1st panel if no selected)" for waveform display 2021-07-03 08:34:38 +02:00
tests redraw wire/line/rect/arc/poly rubbers after changing zoom/panning; do not wait for Motion events 2020-12-29 03:45:12 +01:00
xschem_library poweramp.sch fixes in sim commands 2021-07-13 18:37:01 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions