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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 0d3ebf7da9 add simulation menu option to create simulation/ dir under current schematic dir (local_netlist_dir) 2021-02-14 23:18:25 +01:00
XSchemWin windows png/pdf export 2021-01-28 23:09:37 +01:00
doc removed/updated obsolete keybinding descriptions, removed status check on Delete key events 2021-01-13 13:44:57 +01:00
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src add simulation menu option to create simulation/ dir under current schematic dir (local_netlist_dir) 2021-02-14 23:18:25 +01:00
tests redraw wire/line/rect/arc/poly rubbers after changing zoom/panning; do not wait for Motion events 2020-12-29 03:45:12 +01:00
xschem_library bus_connect_nolab.sym type set to "show_label" so it will be highlighted when net is highlighted, without needing to set "auto-highlight nets/pins". 2021-02-10 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions