154 lines
3.8 KiB
XML
154 lines
3.8 KiB
XML
v {xschem version=3.4.8RC file_version=1.3}
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G {}
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K {}
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V {}
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S {}
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F {}
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E {}
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B 2 600 -930 1340 -590 {flags=graph
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y1=0
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y2=2
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ypos1=-0.021063888
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ypos2=2.0015494
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divy=5
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subdivy=1
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unity=1
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x1=0
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x2=2e-06
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divx=5
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subdivx=1
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xlabmag=1.0
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ylabmag=1.0
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node="clk
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----
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count_out; count_out3,count_out2,count_out1,count_out0
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---
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count_out3
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count_out2
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count_out1
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count_out0"
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color="8 9 11 9 11 11 11 11"
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dataset=-1
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unitx=1
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logx=0
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logy=0
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digital=1}
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B 2 600 -1260 1340 -930 {flags=graph
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y1=0
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y2=0.43
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=0
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x2=2e-06
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divx=5
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subdivx=1
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xlabmag=1.0
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ylabmag=1.0
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dataset=-1
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unitx=1
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logx=0
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logy=0
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color=4
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node=i(vamm)
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hilight_wave=-1}
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T {These capacitors are used to force
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auto-creation of dac bridges
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(digital count_out --> analog count_out).
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Analog nodes can be plotted and saved
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in raw file.} 880 -400 0 0 0.3 0.3 {layer=7}
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N 70 -230 70 -210 {lab=CLK}
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N 410 -430 460 -430 {lab=CLK}
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N 820 -430 860 -430 {bus=1 lab=count_out[3..0]}
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N 820 -430 820 -390 {lab=count_out[3..0]}
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N 1210 -150 1210 -130 {lab=SUM}
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N 790 -150 1210 -150 {lab=SUM}
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N 790 -240 790 -210 {lab=count_out3}
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N 910 -240 910 -210 {lab=count_out2}
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N 1030 -240 1030 -210 {lab=count_out1}
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N 1150 -240 1150 -210 {lab=count_out0}
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N 600 -430 820 -430 {bus=1 lab=count_out[3..0]}
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C {vsource.sym} 70 -180 0 0 {name=VCLOCK value="pulse 0 'VDD' 49995p 10p 10p 49990p 100n"}
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C {lab_pin.sym} 70 -150 0 0 {name=p6 lab=0}
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C {lab_pin.sym} 70 -230 0 0 {name=p13 lab=CLK}
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C {code_shown.sym} 0 -1110 0 0 {name=COMMANDS only_toplevel=false value="
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.param VDD=1.8
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.control
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**** change default parameters of auto adc/dac bridges
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pre_set auto_bridge_d_in =
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+ ( \\".model auto_adc adc_bridge(
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+ in_low = '0.9 * 1.8 / 2' in_high = '1.1 * 1.8 / 2'
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+ rise_delay=1e-11 fall_delay=1e-11 )\\"
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+ \\"auto_bridge%d [ %s ] [ %s ] auto_adc\\" )
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pre_set auto_bridge_d_out =
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+ ( \\".model auto_dac dac_bridge(
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+ out_low = 0 out_high = 1.8
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+ t_rise=1e-11 t_fall=1e-11 )\\"
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+ \\"auto_bridge%d [ %s ] [ %s ] auto_dac\\" )
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save all
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tran 10p 2u
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remzerovec
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write tb_counter_wrapper.raw
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.endc
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"}
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C {launcher.sym} 630 -550 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw tran"
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}
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C {lab_pin.sym} 410 -430 0 0 {name=p3 lab=CLK}
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C {lab_pin.sym} 860 -430 0 1 {name=p4 lab=count_out[3..0]}
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C {counter.sym} 530 -430 0 0 {name=a1 model=counter
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**** put an asteric or any other character before (and no spaces in between)
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**** the model you DON'T want to use:
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***Verilator***
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*device_model=".model counter d_cosim simulation=\\"./counter.so\\" delay=0"
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***Icarus_verilog***
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device_model=".model counter d_cosim simulation=\\"ivlng\\" sim_args=[\\"counter\\"] delay=0"
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tclcommand="edit_file [abs_sym_path counter.v]"}
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C {parax_cap.sym} 820 -380 0 0 {name=C2[3..0] gnd=0 value=1f m=1}
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C {launcher.sym} 1020 -490 0 0 {name=h3
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descr="Verilate Design"
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tclcommand="execute 1 sh -c \\"cd $netlist_dir; ngspice vlnggen [abs_sym_path counter.v]\\""}
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C {launcher.sym} 1020 -530 0 0 {name=h1
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descr="Icarusate Design"
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tclcommand="execute 1 sh -c \\"cd $netlist_dir; iverilog -o counter [abs_sym_path counter.v]\\""
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}
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C {ammeter.sym} 1210 -100 0 0 {name=VAMM savecurrent=0 spice_ignore=0}
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C {lab_pin.sym} 1210 -70 0 0 {name=p35 lab=0}
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C {res.sym} 790 -180 0 0 {name=R4
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value=8
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 790 -240 0 0 {name=p44 lab=count_out3}
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C {res.sym} 910 -180 0 0 {name=R5
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value=16
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 910 -240 0 0 {name=p45 lab=count_out2}
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C {res.sym} 1030 -180 0 0 {name=R6
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value=32
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 1030 -240 0 0 {name=p46 lab=count_out1}
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C {res.sym} 1150 -180 0 0 {name=R7
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value=64
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 1150 -240 0 0 {name=p47 lab=count_out0}
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C {lab_pin.sym} 1210 -150 0 1 {name=p48 lab=SUM}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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