72 lines
3.2 KiB
HTML
72 lines
3.2 KiB
HTML
<!DOCTYPE html>
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<html>
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<head>
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<title>XSCHEM PRESENTATION</title>
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<link rel="stylesheet" type="text/css" href="xschem_man.css" />
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<style type="text/css">
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/* Local styling goes here */
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p{padding: 15px 30px 10px;}
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.content{ background-image:url('xschem_bg2.png');}
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</style>
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</head>
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<body>
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<!-- start of slide -->
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<div class="content">
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<!-- navigation buttons -->
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<a href="tutorial_xschem_slides04.html" class="prev">PREV</a>
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<a href="tutorial_xschem_slides01.html" class="home">UP</a>
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<a href="tutorial_xschem_slides06.html" class="next">NEXT</a>
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<!-- slide title -->
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<h1>FEATURE LIST</h1>
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<div style="float:left; width:49%;">
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<h3 style="text-align:left; max-width: 100%;margin-left:0;font-size: 90%;">
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<table>
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<tr><th>FEATURE</th><th>DESCRIPTION</th></tr>
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<tr><td>File format for schematic and symbol files.</td><td>ASCII</td></tr>
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<tr><td>Multiple schematic /symbol windows.</td><td>Each handled by 1 XSCHEM instance. A crash of one instance does not crash all others. Tabbed and multi-windows interface has been added.</td></tr>
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<tr><td>Clipboard copy / paste (ctrl-c ctrl-v), across hierarchy levels.</td><td>Yes, between different windows too.</td></tr>
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<tr><td>Memory footprint.</td><td>Very low, data purged on hierarchy traversal.</td></tr>
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<tr><td>Undo buffer.</td><td>Yes.</td></tr>
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<tr><td>Scripting language / GUI toolkit</td><td>Tcl / Tk.</td></tr>
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<tr><td>Schematic netlisting.</td><td>SPICE, Verilog, VHDL, Spectre, tEDAx, embedded into XSCHEM and
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using Awk post processors.</td></tr>
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<tr><td>Wire snap to pin.</td><td>Yes.</td></tr>
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<tr><td>Instance pin auto wiring.</td><td>Yes.</td></tr>
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<tr><td>Net auto-router engine.</td><td>No.</td></tr>
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<tr><td>Parametric symbols</td><td>Yes.</td></tr>
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</table>
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</h3>
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</div>
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<div style="float:left; width:49%;">
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<h3 style="text-align:left; max-width: 100%;margin-left:0;font-size: 90%;">
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<table>
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<tr><th>FEATURE</th><th>DESCRIPTION</th></tr>
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<tr><td>Bus notation for nets and components.</td><td>Yes.</td></tr>
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<tr><td>Portability.</td><td>All UNIX systems with Tcl and X11, Windows with VS and Active-Tcl.</td></tr>
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<tr><td>Netlisting performance.</td><td>Extremely fast, Complex system with 59 sub blocks netlisted in VHDL in < 1 second on a Linux laptop.</td></tr>
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<tr><td>Primitive component creation with arbitrary code for VHDL/SPICE/verilog.</td><td>Works out of the box with very simple property strings.</td></tr>
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<tr><td>Single / split file netlisting.</td><td>Yes, any supported netlist formats.</td></tr>
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<tr><td>Mixed mode netlisting, symbol based.</td><td>Yes, in split netlisting mode.</td></tr>
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<tr><td>Automatic symbol creation from schematic and vice-versa.</td><td>Yes.</td></tr>
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<tr><td>Property editing on multiple instances, changing only modified token/value pairs, even on different symbol sets.</td><td>Yes.</td></tr>
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<tr><td>Pin creation from schematic nets.</td><td>Yes, net names can be changed to pins and vice-versa, function to automatically generate pins for nets that are undriven.</td></tr>
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</table>
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</h3>
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</div>
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<!-- end of slide -->
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<div class="filler"></div>
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</div>
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<!-- frame footer -->
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<iframe seamless src="xschem_footer.html" class="footer_iframe" >
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</body>
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</html>
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