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xschem
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add as comments in netlist absolute paths for .sch and .sym of all expanded subcircuits

This commit is contained in:
Stefan Frederik 2021-02-09 23:04:26 +01:00
parent 238c9f592d
commit fd561a9101
4 changed files with 51 additions and 60 deletions
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21
src/spice_netlist.c
View File

@ -321,17 +321,21 @@ void spice_block_netlist(FILE *fd, int i)
spice_stop=1;
else
spice_stop=0;
if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) {
my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename));
} else {
my_strncpy(filename, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), S(filename));
}
if(split_files) {
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d", netlist_dir, skip_dir(xctx->sym[i].name), getpid());
dbg(1, "spice_block_netlist(): split_files: netl_filename=%s\n", netl_filename);
fd=fopen(netl_filename, "w");
my_snprintf(cellname, S(cellname), "%s.spice", skip_dir(xctx->sym[i].name));
}
fprintf(fd, "\n* expanding symbol: %s # of pins=%d\n\n",
fprintf(fd, "\n* expanding symbol: %s # of pins=%d\n",
xctx->sym[i].name,xctx->sym[i].rects[PINLAYER] );
fprintf(fd, "* sym_path: %s\n", abs_sym_path(xctx->sym[i].name, ""));
fprintf(fd, "* sch_path: %s\n", filename);
fprintf(fd, ".subckt %s ",skip_dir(xctx->sym[i].name));
print_spice_subckt(fd, i);
@ -346,14 +350,7 @@ void spice_block_netlist(FILE *fd, int i)
my_free(950, &extra);
fprintf(fd, "\n");
if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) {
my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename));
spice_stop? load_schematic(0,filename, 0) :
load_schematic(1,filename, 0);
} else {
spice_stop? load_schematic(0, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch") ,0) :
load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch") ,0);
}
spice_stop ? load_schematic(0,filename, 0) : load_schematic(1,filename, 0);
spice_netlist(fd, spice_stop); /* 20111113 added spice_stop */
netlist_count++;

20
src/tedax_netlist.c
View File

@ -155,8 +155,15 @@ void tedax_block_netlist(FILE *fd, int i)
tedax_stop=1;
else
tedax_stop=0;
fprintf(fd, "\n# expanding symbol: %s # of pins=%d\n\n",
if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) {
my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename));
} else {
my_strncpy(filename, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), S(filename));
}
fprintf(fd, "\n# expanding symbol: %s # of pins=%d\n",
xctx->sym[i].name,xctx->sym[i].rects[PINLAYER] );
fprintf(fd, "# sym_path: %s\n", abs_sym_path(xctx->sym[i].name, ""));
fprintf(fd, "# sch_path: %s\n", filename);
fprintf(fd, "begin netlist v1 %s\n",skip_dir(xctx->sym[i].name));
print_tedax_subckt(fd, i);
@ -171,16 +178,7 @@ void tedax_block_netlist(FILE *fd, int i)
fprintf(fd, "%s", get_sym_template(xctx->sym[i].templ, extra));
my_free(966, &extra);
fprintf(fd, "\n");
if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) {
my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename));
load_schematic(1,filename, 0);
} else {
dbg(1, "tedax_block_netlist(): loading: %s -> %s\n",
xctx->sym[i].name, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"));
dbg(1, "tedax_block_netlist(): current_dirname=%s\n", xctx->current_dirname);
load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0);
}
load_schematic(1,filename, 0);
tedax_netlist(fd, tedax_stop);
netlist_count++;

50
src/verilog_netlist.c
View File

@ -367,8 +367,11 @@ void verilog_block_netlist(FILE *fd, int i)
verilog_stop=1;
else
verilog_stop=0;
if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) {
my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename));
} else {
my_strncpy(filename, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), S(filename));
}
if(split_files) {
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
netlist_dir, skip_dir(xctx->sym[i].name), getpid());
@ -379,37 +382,30 @@ void verilog_block_netlist(FILE *fd, int i)
}
dbg(1, "verilog_block_netlist(): expanding %s\n", xctx->sym[i].name);
fprintf(fd, "\n// expanding symbol: %s # of pins=%d\n\n",
fprintf(fd, "\n// expanding symbol: %s # of pins=%d\n",
xctx->sym[i].name,xctx->sym[i].rects[PINLAYER] );
fprintf(fd, "// sym_path: %s\n", abs_sym_path(xctx->sym[i].name, ""));
fprintf(fd, "// sch_path: %s\n", filename);
if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) {
my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename));
verilog_stop? load_schematic(0,filename, 0) :
load_schematic(1,filename, 0);
} else {
verilog_stop? load_schematic(0, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0) :
load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0);
}
verilog_stop? load_schematic(0,filename, 0) : load_schematic(1,filename, 0);
/* print verilog timescale and preprocessor directives 10102004 */
for(j=0;j<xctx->instances;j++)
{
if( strcmp(get_tok_value(xctx->inst[j].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[j].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[j].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
my_strdup(544, &type,(xctx->inst[j].ptr+ xctx->sym)->type);
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
str_tmp = get_tok_value( (xctx->inst[j].ptr+ xctx->sym)->prop_ptr ,"verilog_format",0);
my_strdup(545, &tmp_string, str_tmp);
fprintf(fd, "%s\n", str_tmp ? translate(j, tmp_string) : "(NULL)");
}
for(j=0;j<xctx->instances;j++)
{
if( strcmp(get_tok_value(xctx->inst[j].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[j].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[j].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
my_strdup(544, &type,(xctx->inst[j].ptr+ xctx->sym)->type);
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
str_tmp = get_tok_value( (xctx->inst[j].ptr+ xctx->sym)->prop_ptr ,"verilog_format",0);
my_strdup(545, &tmp_string, str_tmp);
fprintf(fd, "%s\n", str_tmp ? translate(j, tmp_string) : "(NULL)");
}
}
fprintf(fd, "module %s (\n", skip_dir(xctx->sym[i].name));
/*print_generic(fd, "entity", i); */

20
src/vhdl_netlist.c
View File

@ -418,7 +418,11 @@ void vhdl_block_netlist(FILE *fd, int i)
vhdl_stop=1;
else
vhdl_stop=0;
if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) {
my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename));
} else {
my_strncpy(filename, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), S(filename));
}
if(split_files) {
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d", netlist_dir, skip_dir(xctx->sym[i].name), getpid());
dbg(1, "vhdl_block_netlist(): split_files: netl_filename=%s\n", netl_filename);
@ -427,18 +431,14 @@ void vhdl_block_netlist(FILE *fd, int i)
}
dbg(1, "vhdl_block_netlist(): expanding %s\n", xctx->sym[i].name);
fprintf(fd, "\n-- expanding symbol: %s # of pins=%d\n\n",
fprintf(fd, "\n-- expanding symbol: %s # of pins=%d\n",
xctx->sym[i].name,xctx->sym[i].rects[PINLAYER] );
fprintf(fd, "-- sym_path: %s\n", abs_sym_path(xctx->sym[i].name, ""));
fprintf(fd, "-- sch_path: %s\n", filename);
if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) {
my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename));
load_schematic(1,filename, 0);
} else {
/* this can not be done im VHDL as vhdl needs "arch_declaration" and "attributes" type instances */
/* vhdl_stop ? load_schematic(0, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0) : */
load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0);
}
load_schematic(1,filename, 0);
dbg(1, "vhdl_block_netlist(): packages\n");
for(l=0;l<xctx->instances;l++)
{