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differential scope2.sym, current mwasure scope_ammeter.sym

This commit is contained in:
stefan schippers 2025-02-24 15:23:35 +01:00
parent b205b4a496
commit f9ccf878c2
12 changed files with 296 additions and 39 deletions
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11
doc/xschem_man/developer_info.html
View File

@ -551,7 +551,6 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
<li><kbd> abort_operation</kbd></li><pre>
@ -828,6 +827,15 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
return result of get_cell function </pre>
<li><kbd> get_cell_w_ext cell n_dirs</kbd></li><pre>
return result of get_cell_w_ext function </pre>
<li><kbd> get_fqdevice instname param modelparam</kbd></li><pre>
get the full pathname of "instname" device
modelparam:
0: current, 1: modelparam, 2: modelvoltage
param: device parameter, like ib, gm, vth
set param to {} (empty str) for just branch current of 2 terminal device
for parameters like "vth" modelparam must be 2
for parameters like "ib" modelparam must be 0
for parameters like "gm" modelparam must be 1</pre>
<li><kbd> getprop instance|instance_pin|symbol|text ref</kbd></li><pre>
getprop instance inst
@ -1735,6 +1743,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
</ul>

44
src/actions.c
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@ -1450,7 +1450,6 @@ void delete_files(void)
void place_net_label(int type)
{
unselect_all(1);
if(type == 1) {
const char *lab = tcleval("rel_sym_path [find_file_first lab_pin.sym]");
place_symbol(-1, lab, xctx->mousex_snap, xctx->mousey_snap, 0, 0, NULL, 4, 1, 1/*to_push_undo*/);
@ -1478,6 +1477,7 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
char name[PATH_MAX];
char name1[PATH_MAX];
char tclev = 0;
if(symbol_name==NULL) {
tcleval("load_file_dialog {Choose symbol} *.\\{sym,tcl\\} INITIALINSTDIR");
my_strncpy(name1, tclresult(), S(name1));
@ -1562,7 +1562,11 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
/* After having assigned prop_ptr to new instance translate symbol reference
* to resolve @params --> res.tcl(@value\) --> res.tcl(100) */
my_strncpy(name, translate(n, name), S(name));
i = match_symbol(name);
/* parameters like res.tcl(@value\) have been resolved, so reload symbol removing previous */
if(strcmp(name, name1)) {
remove_symbol(i);
i = match_symbol(name);
}
xctx->inst[n].ptr = i;
set_inst_flags(&xctx->inst[n]);
hash_names(n, XINSERT);
@ -1579,15 +1583,44 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
/* embed a (locked) graph object floater inside the symbol */
if(xctx->sym[i].type && !strcmp(xctx->sym[i].type, "scope")) {
char *prop = NULL;
my_strdup(_ALLOC_ID_, &xctx->inst[n].prop_ptr,
subst_token(xctx->inst[n].prop_ptr, "attach", xctx->inst[n].instname));
my_mstrcat(_ALLOC_ID_, &prop, "name=", xctx->inst[n].instname, "\n", NULL);
my_mstrcat(_ALLOC_ID_, &prop, "flags=graph,unlocked\n", NULL);
my_mstrcat(_ALLOC_ID_, &prop, "lock=1\n", NULL);
my_mstrcat(_ALLOC_ID_, &prop, "color=8\n", NULL);
my_mstrcat(_ALLOC_ID_, &prop, "node=\"tcleval([xschem translate ",
xctx->inst[n].instname, " @#0:net_name])\"", NULL);
storeobject(-1, x-130, y-120, x - 20, y - 40, xRECT, 2, SELECTED, prop);
if(xctx->sym[i].rects[PINLAYER] == 0) {
if(xctx->lastsel == 1 && xctx->sel_array[0].type==ELEMENT) {
my_mstrcat(_ALLOC_ID_, &prop, "node=\"tcleval([xschem get_fqdevice [xschem translate ",
xctx->inst[n].instname, " @device]])\"\n", NULL);
my_strdup(_ALLOC_ID_, &xctx->inst[n].prop_ptr,
subst_token(xctx->inst[n].prop_ptr, "device", xctx->inst[xctx->sel_array[0].n].instname));
} else {
const char msg[]="scope_ammeter is being inserted but no selected ammeter device/vsource to link to\n";
dbg(0, "%s", msg);
if(has_x) tclvareval("alert_ {", msg, "} {}", NULL);
if(xctx->inst[n].instname) my_free(_ALLOC_ID_, &xctx->inst[n].instname);
if(xctx->inst[n].name) my_free(_ALLOC_ID_, &xctx->inst[n].name);
if(xctx->inst[n].prop_ptr) my_free(_ALLOC_ID_, &xctx->inst[n].prop_ptr);
if(xctx->inst[n].lab) my_free(_ALLOC_ID_, &xctx->inst[n].lab);
if(prop) my_free(_ALLOC_ID_, &prop);
xctx->instances--;
return 0;
}
} else if(xctx->sym[i].rects[PINLAYER] == 1) {
my_mstrcat(_ALLOC_ID_, &prop,
"node=\"tcleval(",
"[xschem translate ", xctx->inst[n].instname, " @#0:net_name]",
")\"\n", NULL);
} else {
my_mstrcat(_ALLOC_ID_, &prop,
"node=\"tcleval(",
"[xschem translate ", xctx->inst[n].instname, " @#0:net_name] ",
"[xschem translate ", xctx->inst[n].instname, " @#1:net_name] -",
")\"\n", NULL);
}
storeobject(-1, x + 20, y-125, x + 130 , y - 25, xRECT, 2, SELECTED, prop);
my_free(_ALLOC_ID_, &prop);
}
@ -1602,6 +1635,7 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
/* hilight new element 24122002 */
if(draw_sym & 4 ) {
unselect_all(1);
select_element(n, SELECTED,0, 1);
drawtemparc(xctx->gc[SELLAYER], END, 0.0, 0.0, 0.0, 0.0, 0.0);
drawtemprect(xctx->gc[SELLAYER], END, 0.0, 0.0, 0.0, 0.0);

1
src/callback.c
View File

@ -202,7 +202,6 @@ static void start_place_symbol(void)
tclvareval("set INITIALINSTDIR [file dirname {",
abs_sym_path(tcl_hook2(xctx->inst[xctx->sel_array[0].n].name), ""), "}]", NULL);
}
unselect_all(1);
xctx->mx_double_save = xctx->mousex_snap;
xctx->my_double_save = xctx->mousey_snap;
if(place_symbol(-1,NULL,xctx->mousex_snap, xctx->mousey_snap, 0, 0, NULL, 4, 1, 1/* to_push_undo */) ) {

2
src/move.c
View File

@ -540,7 +540,7 @@ void update_attached_floaters(const char *from_name, int inst, int sel)
if(c == GRIDLAYER) {
const char *node = get_tok_value(xctx->rect[c][i].prop_ptr, "node", 2);
if(node && node[0]) {
const char *new_node = str_replace(node, from_name, to_name, 1, 1);
const char *new_node = str_replace(node, from_name, to_name, 1, -1);
my_strdup(_ALLOC_ID_, &xctx->rect[c][i].prop_ptr,
subst_token(xctx->rect[c][i].prop_ptr, "node", new_node));
}

29
src/scheduler.c
View File

@ -1798,8 +1798,34 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_SetResult(interp, (char *)get_cell_w_ext(argv[2], atoi(argv[3])), TCL_VOLATILE);
}
}
/************ end xschem get subcommands *************/
/* get_fqdevice instname param modelparam
* get the full pathname of "instname" device
* modelparam:
* 0: current, 1: modelparam, 2: modelvoltage
* param: device parameter, like ib, gm, vth
* set param to {} (empty str) for just branch current of 2 terminal device
* for parameters like "vth" modelparam must be 2
* for parameters like "ib" modelparam must be 0
* for parameters like "gm" modelparam must be 1
*/
else if(!strcmp(argv[1], "get_fqdevice"))
{
char *fqdev;
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
if(argc > 4) {
fqdev = get_fqdevice(argv[3], atoi(argv[4]), argv[2]);
Tcl_SetResult(interp, fqdev, TCL_VOLATILE);
my_free(_ALLOC_ID_, &fqdev);
} else if(argc > 2) {
fqdev = get_fqdevice("", 0, argv[2]);
Tcl_SetResult(interp, fqdev, TCL_VOLATILE);
my_free(_ALLOC_ID_, &fqdev);
}
}
/* getprop instance|instance_pin|symbol|text ref
*
* getprop instance inst
@ -3605,7 +3631,6 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
tclvareval("set INITIALINSTDIR [file dirname {",
abs_sym_path(tcl_hook2(xctx->inst[xctx->sel_array[0].n].name), ""), "}]", NULL);
}
unselect_all(1);
xctx->mx_double_save = xctx->mousex_snap;
xctx->my_double_save = xctx->mousey_snap;
if(argc > 3) {

94
src/token.c
View File

@ -184,6 +184,7 @@ int match_symbol(const char *name) /* never returns -1, if symbol not found loa
int i,found;
found=0;
dbg(1, "match_symbol(): name=%s\n", name);
for(i=0;i<xctx->symbols; ++i) {
/* dbg(1, "match_symbol(): name=%s, sym[i].name=%s\n",name, xctx->sym[i].name);*/
if(xctx->x_strcmp(name, xctx->sym[i].name) == 0)
@ -3779,6 +3780,99 @@ const char *spice_get_node(const char *token)
}
/* caller must free returned value
* get the full pathname of "instname" device
* modelparam:
* 0: current, 1: modelparam, 2: modelvoltage
* param: device parameter, like "ib", "gm", "vth"
* set param to {} (empty str) for just branch current of 2 terminal device
* for parameters like "vth" modelparam must be 2
* for parameters like "ib" modelparam must be 0
* for parameters like "gm" modelparam must be 1
*/
char *get_fqdevice(const char *param, int modelparam, const char *instname)
{
int start_level; /* hierarchy level where waves were loaded */
char *fqdev = NULL;
const char *path = xctx->sch_path[xctx->currsch] + 1;
char *dev = NULL;
size_t len;
int idx;
int sim_is_xyce = tcleval("sim_is_xyce")[0] == '1' ? 1 : 0;
int skip = 0;
char *iprefix = modelparam == 0 ? "i(" : modelparam == 1 ? "" : "v(";
char *ipostfix = modelparam == 1 ? "" : ")";
int prefix;
start_level = sch_waves_loaded();
/* skip path components that are above the level where raw file was loaded */
while(*path && skip < start_level) {
if(*path == '.') skip++;
++path;
}
my_strdup2(_ALLOC_ID_, &dev, instname);
strtolower(dev);
prefix=dev[0];
len = strlen(path) + strlen(dev) + 40; /* some extra chars for i(..) wrapper */
fqdev = my_malloc(_ALLOC_ID_, len);
if(!sim_is_xyce) {
int vsource = (prefix == 'v') || (prefix == 'e');
if(path[0]) {
if(vsource) {
my_snprintf(fqdev, len, "i(%c.%s%s)", prefix, path, dev);
} else if(prefix=='q') {
my_snprintf(fqdev, len, "%s@%c.%s%s[%s]%s",
iprefix, prefix, path, dev, param ? param : "ic", ipostfix);
} else if(prefix=='d' || prefix == 'm') {
my_snprintf(fqdev, len, "%s@%c.%s%s[%s]%s",
iprefix, prefix, path, dev, param ? param : "id", ipostfix);
} else if(prefix=='i') {
my_snprintf(fqdev, len, "i(@%c.%s%s[current])", prefix, path, dev);
} else {
my_snprintf(fqdev, len, "i(@%c.%s%s[i])", prefix, path, dev);
}
} else {
if(vsource) {
my_snprintf(fqdev, len, "i(%s)", dev);
} else if(prefix == 'q') {
my_snprintf(fqdev, len, "%s@%s[%s]%s", iprefix, dev, param ? param : "ic", ipostfix);
} else if(prefix == 'd' || prefix == 'm') {
my_snprintf(fqdev, len, "%s@%s[%s]%s", iprefix, dev, param ? param : "id", ipostfix);
} else if(prefix == 'i') {
my_snprintf(fqdev, len, "i(@%s[current])", dev);
} else {
my_snprintf(fqdev, len, "i(@%s[i])", dev);
}
}
} else {
my_snprintf(fqdev, len, "i(%s%s)", path, dev);
}
dbg(1, "fqdev=%s\n", fqdev);
strtolower(fqdev);
idx = get_raw_index(fqdev, NULL);
/* special handling for resistors that are converted to b sources:
* i(@r.x4.r1[i]) --> i(@b.x4.br1[i])
*/
if(idx < 0 && !strncmp(fqdev, "i(@r", 4)) {
if(path[0]) {
my_snprintf(fqdev, len, "i(@b.%sb%s[i])", path, dev);
} else {
my_snprintf(fqdev, len, "i(@b%s[i])", dev);
}
dbg(1, "fqdev=%s\n", fqdev);
}
my_free(_ALLOC_ID_, &dev);
return fqdev;
}
/* substitute given tokens in a string with their corresponding values */
/* ex.: name=@name w=@w l=@l ---> name=m112 w=3e-6 l=0.8e-6 */
/* if s==NULL return emty string */

1
src/xschem.h
View File

@ -1613,6 +1613,7 @@ extern char *trim_chars(const char *str, const char *sep);
extern char *find_nth(const char *str, const char *sep, const char *quote, int keep_quote, int n);
extern int isonlydigit(const char *s);
extern const char *spice_get_node(const char *token);
extern char *get_fqdevice(const char *param, int modelparam, const char *instname);
extern const char *translate(int inst, const char* s);
extern const char* translate2(Lcc *lcc, int level, char* s);
extern const char *translate3(const char* s, int eat_escapes, const char *s1,

8
xschem_library/devices/scope.sym
View File

@ -26,8 +26,8 @@ highlight=true}
V {}
S {}
E {}
L 4 -10 -20 0 0 {}
L 4 0 0 10 -20 {}
B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
P 4 5 -140 -20 -140 -140 -10 -140 -10 -20 -140 -20 {}
T {@#0:net_name} -12.5 -35.625 0 1 0.2 0.2 {layer=4}
T {@spice_get_voltage} -137.5 -137.5 0 0 0.2 0.2 {layer=15}
P 4 5 10 -20 10 -140 140 -140 140 -20 10 -20 {}
T {@#0:net_name} 12.5 -18.125 0 0 0.2 0.2 {layer=4}
T {@#0:spice_get_voltage} 12.5 -139.375 0 0 0.15 0.15 {layer=15}

36
xschem_library/devices/scope2.sym Normal file
View File

@ -0,0 +1,36 @@
v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=scope
template="name=l1"
highlight=true}
V {}
S {}
E {}
L 4 0 0 10 -20 {}
L 4 0 -160 10 -140 {}
B 5 -1.25 -161.25 1.25 -158.75 {name=p dir=in}
B 5 -1.25 -1.25 1.25 1.25 {name=m dir=in}
P 4 5 10 -20 10 -140 140 -140 140 -20 10 -20 {}
T {@#1:net_name} 12.5 -18.125 0 0 0.2 0.2 {layer=4}
T {@#0:net_name} 12.5 -153.125 0 0 0.2 0.2 {layer=4}
T {@spice_get_diff_voltage} 12.5 -139.375 0 0 0.15 0.15 {layer=15}

31
xschem_library/devices/scope_ammeter.sym Normal file
View File

@ -0,0 +1,31 @@
v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=scope
template="name=l1"
highlight=true}
V {}
S {}
E {}
P 4 5 10 -20 10 -140 140 -140 140 -20 10 -20 {}
T {@device} 12.5 -18.125 0 0 0.2 0.2 {layer=4}
T {tcleval(@spice_get_node [xschem get_fqdevice @device ] )} 12.5 -139.375 0 0 0.15 0.15 {layer=15}

14
xschem_library/ngspice/comp_ngspice.sch
View File

@ -1,4 +1,4 @@
v {xschem version=3.4.6RC file_version=1.2
v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -24,6 +24,15 @@ K {}
V {}
S {}
E {}
B 2 520 -415 630 -315 {name=l4
flags=graph,unlocked
lock=1
color=8
node="tcleval([xschem get_fqdevice [xschem translate l4 @device]])"
y1=-0.00014
y2=0.00013
x1=0.00044464632
x2=0.00046163671}
T {( @#0:resolved_net )} 440 -265 0 1 0.2 0.2 {name=l2 layer=15}
T {( @#0:resolved_net )} 100 -285 0 1 0.2 0.2 {name=p1 layer=15}
T {( @#0:resolved_net )} 100 -235 0 1 0.2 0.2 {name=p2 layer=15}
@ -49,3 +58,6 @@ m=1}
C {parax_cap.sym} 630 -230 0 0 {name=C3 gnd=0 value=\{COUT\} m=1}
C {vsource.sym} 150 -260 1 0 {name=V1 value=0}
C {vsource.sym} 150 -210 1 0 {name=V2 value=0}
C {scope_ammeter.sym} 500 -290 0 0 {name=l4
attach=l4
device=R1}

64
xschem_library/ngspice/solar_panel.sch
View File

@ -193,16 +193,16 @@ autoload=0
sim_type=tran
xrawfile=$netlist_dir/solar_panel.raw}
B 2 270 -730 380 -650 {name=l21
B 2 1210 -605 1320 -505 {name=l21
flags=graph,unlocked
lock=1
color=8
node="tcleval([xschem translate l21 @#0:net_name])"
y1=0.00033
y2=21
node="tcleval([xschem translate l21 @#0:net_name] [xschem translate l21 @#1:net_name] -)"
x1=5e-10
x2=0.001}
B 2 1230 -560 1340 -480 {name=l22
x2=0.001
y1=-4.8
y2=15}
B 2 400 -735 510 -635 {name=l22
flags=graph,unlocked
lock=1
color=8
@ -211,15 +211,24 @@ y1=0.00033
y2=21
x1=5e-10
x2=0.001}
B 2 780 -1200 890 -1120 {name=l23
B 2 600 -485 710 -385 {name=l23
flags=graph,unlocked
lock=1
color=8
node="tcleval([xschem translate l23 @#0:net_name])"
y1=-0.55990715
y2=1.5136929
x1=0.00048981872
x2=0.0005150806}
node="tcleval([xschem get_fqdevice [xschem translate l23 @device]])"
x1=5e-10
x2=0.001
y1=-2.9
y2=6.8}
B 2 640 -295 750 -195 {name=l26
flags=graph,unlocked
lock=1
color=8
node="tcleval([xschem get_fqdevice [xschem translate l26 @device]])"
x1=5e-10
x2=0.001
y1=-2.9
y2=6.8}
B 18 55 -1060 310 -875 {}
A 5 310 -1060 5.590169943749475 243.434948822922 360 {fill=true}
P 7 6 385 -875 330 -1031.25 325 -1045 312.5 -1060 300 -1065 55 -1075 {}
@ -259,19 +268,19 @@ T {Floater text
example} 870 -440 0 0 0.4 0.4 {}
T {@spice_get_current} 875 -598.75 0 0 0.3 0.3 {layer=7 name=L2}
T {@spice_get_current} 1015 -268.75 0 0 0.3 0.3 {layer=7 name=C1}
N 1010 -210 1100 -210 {lab=0}
N 1100 -300 1100 -210 {lab=0}
N 1010 -180 1100 -180 {lab=0}
N 1100 -300 1100 -180 {lab=0}
N 640 -610 730 -610 {lab=#net1}
N 1010 -440 1040 -440 {lab=VO}
N 1010 -440 1010 -310 {lab=VO}
N 1010 -250 1010 -210 {lab=0}
N 1010 -250 1010 -180 {lab=0}
N 360 -610 580 -610 {lab=PANEL}
N 1010 -610 1010 -440 {lab=VO}
N 820 -610 860 -610 {lab=SW}
N 820 -610 820 -490 {lab=SW}
N 790 -610 820 -610 {lab=SW}
N 820 -210 1010 -210 {lab=0}
N 800 -210 820 -210 {lab=0}
N 820 -180 1010 -180 {lab=0}
N 800 -180 820 -180 {lab=0}
N 1000 -610 1010 -610 {lab=VO}
N 1100 -440 1280 -440 {lab=LED}
N 1100 -440 1100 -360 {lab=LED}
@ -322,10 +331,12 @@ N 770 -1080 770 -1030 {
lab=TRIANG}
N 770 -1030 890 -1030 {
lab=TRIANG}
N 820 -330 820 -210 {
N 820 -330 820 -180 {
lab=0}
N 1190 -480 1190 -440 {lab=LED}
N 1190 -670 1190 -640 {lab=PANEL}
C {title.sym} 160 -40 0 0 {name=l1 author="Stefan Schippers"}
C {code_shown.sym} 170 -310 0 0 {name=CONTROL
C {code_shown.sym} 180 -310 0 0 {name=CONTROL
value="tcleval(
.option savecurrents
.control
@ -345,7 +356,7 @@ C {code.sym} 20 -240 0 0 {name=MODELS value=".MODEL DIODE D(IS=1.139e-08 RS=0.99
.MODEL swmod SW(VT=0.5 VH=0.01 RON=0.01 ROFF=10000000)
"}
C {lab_pin.sym} 650 -530 0 1 {name=l4 lab=PANEL }
C {lab_pin.sym} 800 -210 0 0 {name=l6 lab=0 }
C {lab_pin.sym} 800 -180 0 0 {name=l6 lab=0 }
C {ammeter.sym} 1070 -440 3 0 {name=Vled}
C {ind.sym} 890 -610 3 1 {name=L2
m=1
@ -433,9 +444,14 @@ C {spice_probe.sym} 810 -890 0 1 {name=p5 analysis=tran}
C {spice_probe.sym} 760 -670 0 0 {name=p6 analysis=tran}
C {spice_probe.sym} 160 -450 0 0 {name=p7 analysis=tran}
C {lab_show.sym} 440 -610 2 0 {name=l24}
C {scope.sym} 400 -610 0 0 {name=l21
C {lab_pin.sym} 1190 -670 0 0 {name=l25 lab=PANEL }
C {scope2.sym} 1190 -480 0 0 {name=l21
attach=l21}
C {scope.sym} 1210 -440 0 1 {name=l22
C {scope.sym} 380 -610 0 0 {name=l22
attach=l22}
C {scope.sym} 760 -1080 0 1 {name=l23
attach=l23}
C {scope_ammeter.sym} 580 -360 0 0 {name=l23
attach=l23
device=Vcap}
C {scope_ammeter.sym} 620 -170 0 0 {name=l26
attach=l26
device=Vdiode}