fixed is_symgen() regex, added stup for tutorial_symbol_generators.html
This commit is contained in:
parent
d5aca937ce
commit
f1ed2bf26f
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@ -0,0 +1,29 @@
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<!DOCTYPE html>
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<html>
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<head>
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<title>XSCHEM TUTORIAL: SYMBOL GENERATORS</title>
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<link rel="stylesheet" type="text/css" href="xschem_man.css" />
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<style type="text/css">
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/* Local styling goes here */
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p{padding: 15px 30px 10px;}
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</style>
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</head>
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<body>
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<!-- start of slide -->
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<div class="content">
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<!-- navigation buttons -->
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<a href="xschem_man.html" class="home">UP</a>
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<!-- slide title -->
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<h1> TUTORIAL: SYMBOL GENERATORS</h1>
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<!-- end of slide -->
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<div class="filler"></div>
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</div>
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<!-- frame footer -->
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<iframe seamless src="xschem_footer.html" class="footer_iframe" >
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</body>
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</html>
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@ -57,6 +57,7 @@
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<li><a href="tutorial_install_xschem.html">Step by step instructions: Install XSCHEM</a></li>
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<li><a href="tutorial_run_simulation.html">Run a simulation with XSCHEM</a></li>
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<li><a href="tutorial_instance_based_implementation.html">Instance based selection of symbol implementation</a></li>
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<li><a href="tutorial_symbol_generators.html">Symbol generators</a></li>
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<li><a href="tutorial_use_existing_subckt.html">Create a symbol and use an existing subcircuit netlist</a></li>
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<li><a href="tutorial_create_symbol.html">Create a symbol with XSCHEM</a></li>
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<li><a href="tutorial_xschem_libraries.html">Manage XSCHEM design libraries / symbol librares</a></li>
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@ -1765,6 +1765,17 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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Tcl_SetResult(interp, pins ? pins : "", TCL_VOLATILE);
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my_free(_ALLOC_ID_, &pins);
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}
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/* is_symgen symbol
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* tell if 'symbol' is agenerator (symbol(param1,param2,...) */
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else if(!strcmp(argv[1], "is_symgen"))
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{
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char s[30];
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if(argc > 2) {
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my_snprintf(s, S(s), "%d", is_symgen(argv[2]));
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Tcl_SetResult(interp, s, TCL_VOLATILE);
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}
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}
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else { cmd_found = 0;}
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break;
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case 'l': /*----------------------------------------------*/
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@ -176,9 +176,10 @@ int is_symgen(const char *name)
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}
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if(!re) {
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re = my_malloc(_ALLOC_ID_, sizeof(regex_t));
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regcomp(re, "^[^ \\t()]+\\([^()]*\\)[ \\t]*$", REG_NOSUB | REG_EXTENDED);
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regcomp(re, "^[^ \t()]+\\([^()]*\\)[ \t]*$", REG_NOSUB | REG_EXTENDED);
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}
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if(!regexec(re, name, 0 , NULL, 0) ) res = 1;
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dbg(1, "is_symgen(%s)=%d\n", name, res);
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/* regfree(&re); */
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return res;
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#else
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@ -202,9 +203,10 @@ int match_symbol(const char *name) /* never returns -1, if symbol not found loa
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}
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if(!found)
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{
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dbg(1, "match_symbol(): matching symbol not found:%s, loading\n",name);
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dbg(1, "match_symbol(): matching symbol not found: loading\n");
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if(!is_symgen(name)) {
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dbg(1, "match_symbol(): symbol=%s\n",name);
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load_sym_def(name, NULL, 0); /* append another symbol to the xctx->sym[] array */
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} else { /* get symbol from generator script */
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FILE *fp;
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@ -214,6 +216,7 @@ int match_symbol(const char *name) /* never returns -1, if symbol not found loa
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char *spc_idx;
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struct stat buf;
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dbg(1, "match_symbol(): symgen=%s\n",name);
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cmd = str_chars_replace(name, " (),", ' ');
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spc_idx = strchr(cmd, ' ');
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if(!spc_idx) goto end;
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@ -1,4 +1,5 @@
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v {xschem version=3.0.0 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {}
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V {}
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@ -102,16 +103,19 @@ C {ipin.sym} 640 -190 0 0 {name=p10 lab=CK}
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C {ipin.sym} 640 -150 0 0 {name=p11 lab=RST}
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C {lab_pin.sym} 790 -170 0 0 {name=p14 lab=VCC}
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C {lab_pin.sym} 950 -190 0 1 {name=p24 lab=C[5:0]}
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C {and3_ngspice.sym} 1120 -230 0 0 {name=x5 ROUT=1000}
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C {and3_ngspice.sym} 1120 -230 0 0 {name=x5 ROUT=1000 net_name=true}
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C {lab_pin.sym} 1080 -250 0 0 {name=p25 lab=C[5]}
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C {lab_pin.sym} 1080 -230 0 0 {name=p26 lab=C[4]}
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C {lab_pin.sym} 1080 -210 0 0 {name=p27 lab=C[3]}
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C {lab_pin.sym} 1080 -150 0 0 {name=p28 lab=C[1]}
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C {lab_pin.sym} 1080 -130 0 0 {name=p29 lab=C[0]}
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C {and3_ngspice.sym} 1120 -150 0 0 {name=x6 ROUT=1000}
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C {and3_ngspice.sym} 1120 -150 0 0 {name=x6 ROUT=1000
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net_name=true}
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C {lab_pin.sym} 1080 -170 0 0 {name=p30 lab=C[2]}
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C {and_ngspice.sym} 1220 -190 0 0 {name=x7 ROUT=1000}
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C {or_ngspice.sym} 1320 -210 0 0 {name=x8 ROUT=1000}
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C {and_ngspice.sym} 1220 -190 0 0 {name=x7 ROUT=1000
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net_name=true}
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C {or_ngspice.sym} 1320 -210 0 0 {name=x8 ROUT=1000
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net_name=true}
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C {lab_pin.sym} 1280 -230 0 0 {name=p31 lab=RST}
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C {lab_pin.sym} 1540 -230 0 1 {name=p15 lab=RSTI}
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C {flip_flop_ngspice.sym} 1480 -210 0 0 {name=x9}
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@ -121,7 +125,7 @@ C {lab_pin.sym} 1520 -390 0 0 {name=p1 lab=RST}
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C {spice_probe.sym} 840 -250 0 0 {name=p6 attrs=""}
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C {spice_probe.sym} 710 -410 0 0 {name=p17 attrs=""}
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C {spice_probe.sym} 1540 -270 0 0 {name=p18 attrs=""}
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C {inv_ngspice.sym} 1040 -410 0 0 {name=x11 ROUT=1000}
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C {inv_ngspice.sym} 1040 -410 0 0 {name=x11 ROUT=1000 net_name=true}
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C {lab_wire.sym} 1130 -410 0 0 {name=l2 lab=QN}
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C {spice_probe.sym} 1090 -410 0 0 {name=p19 attrs=""}
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C {ipin.sym} 310 -370 0 0 {name=p242 lab=VREF}
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@ -145,4 +149,4 @@ C {spice_probe.sym} 220 -430 0 0 {name=p265 attrs=""}
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C {opamp_65nm.sym} 380 -400 2 1 {name=x41}
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C {comp_65nm.sym} 610 -410 0 0 {name=x42}
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C {spice_probe.sym} 1470 -430 0 0 {name=p2 attrs=""}
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C {or_ngspice.sym} 1110 -320 0 0 {name=x3 ROUT=1000}
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C {or_ngspice.sym} 1110 -320 0 0 {name=x3 ROUT=1000 net_name=true}
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@ -1,4 +1,5 @@
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v {xschem version=2.9.9 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {}
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V {}
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@ -18,7 +19,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((min(V(C1),min(
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C {lab_pin.sym} 310 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
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C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
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C {res.sym} 580 -400 1 0 {name=R1
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value='ROUT'
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value=ROUT
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footprint=1206
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device=resistor
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m=1}
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@ -1,4 +1,5 @@
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v {xschem version=2.9.9 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname ROUT=@ROUT"
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@ -19,3 +20,7 @@ B 5 -42.5 -2.5 -37.5 2.5 {name=B dir=in}
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B 5 -42.5 17.5 -37.5 22.5 {name=C dir=in}
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A 4 5 0 30 270 180 {}
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T {@name} -16.25 -5 0 0 0.2 0.2 {}
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T {@#1:net_name} -22.5 -17.5 0 1 0.15 0.15 {layer=15}
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T {@#0:net_name} 35 1.25 0 0 0.15 0.15 {layer=15}
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T {@#2:net_name} -22.5 2.5 0 1 0.15 0.15 {layer=15}
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T {@#3:net_name} -22.5 22.5 0 1 0.15 0.15 {layer=15}
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@ -1,4 +1,5 @@
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v {xschem version=2.9.9 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {}
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V {}
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@ -17,7 +18,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((min(V(A1),V(B1
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C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
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C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
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C {res.sym} 580 -400 1 0 {name=R1
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value='ROUT'
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value=ROUT
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footprint=1206
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device=resistor
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m=1}
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@ -1,4 +1,5 @@
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v {xschem version=2.9.9 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname ROUT=@ROUT"
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@ -17,3 +18,6 @@ B 5 -42.5 -22.5 -37.5 -17.5 {name=A dir=in}
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B 5 -42.5 17.5 -37.5 22.5 {name=B dir=in}
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A 4 5 0 30 270 180 {}
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T {@name} -16.25 -5 0 0 0.2 0.2 {}
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T {@#1:net_name} -22.5 -17.5 0 1 0.15 0.15 {layer=15}
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T {@#0:net_name} 35 1.25 0 0 0.15 0.15 {layer=15}
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T {@#3:net_name} -22.5 22.5 0 1 0.15 0.15 {layer=15}
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@ -1,4 +1,5 @@
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v {xschem version=2.9.9 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {}
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V {}
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@ -17,7 +18,7 @@ C {bsource.sym} 470 -400 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((V(A1)-VCC/2)*1
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C {lab_pin.sym} 320 -470 0 0 {name=l2 sig_type=std_logic lab=A1}
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C {lab_pin.sym} 470 -320 0 0 {name=l3 sig_type=std_logic lab=0}
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C {res.sym} 570 -470 1 0 {name=R1
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value='ROUT'
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value=ROUT
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footprint=1206
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device=resistor
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m=1}
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@ -1,4 +1,5 @@
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v {xschem version=2.9.9 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname ROUT=@ROUT"
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@ -19,3 +20,5 @@ T {@name} 25 -22 0 0 0.2 0.2 {}
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T {Y} 7.5 -6.5 0 1 0.2 0.2 {}
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T {A} -17.5 -6.5 0 0 0.2 0.2 {}
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T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {}
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T {@#1:net_name} -22.5 6.25 0 1 0.15 0.15 {layer=15}
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T {@#0:net_name} 17.5 6.25 0 0 0.15 0.15 {layer=15}
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@ -1,4 +1,5 @@
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v {xschem version=2.9.9 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {}
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V {}
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@ -17,7 +18,7 @@ C {bsource.sym} 470 -400 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1-tanh((V(A1)-VCC/2)*1
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C {lab_pin.sym} 320 -470 0 0 {name=l2 sig_type=std_logic lab=A1}
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C {lab_pin.sym} 470 -320 0 0 {name=l3 sig_type=std_logic lab=0}
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C {res.sym} 570 -470 1 0 {name=R1
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value='ROUT'
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value=ROUT
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footprint=1206
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device=resistor
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m=1}
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@ -25,5 +25,5 @@ T {@name} 25 -22 0 0 0.2 0.2 {}
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T {Y} 7.5 -6.5 0 1 0.2 0.2 {}
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T {A} -17.5 -6.5 0 0 0.2 0.2 {}
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T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {}
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T {@#1:net_name} -40 6.25 0 0 0.15 0.15 {layer=15}
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T {@#0:net_name} 40 6.25 0 1 0.15 0.15 {layer=15}
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T {@#1:net_name} -22.5 6.25 0 1 0.15 0.15 {layer=15}
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T {@#0:net_name} 17.5 6.25 0 0 0.15 0.15 {layer=15}
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@ -1,4 +1,5 @@
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v {xschem version=2.9.9 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname ROUT=@ROUT"
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@ -18,3 +19,6 @@ A 4 -65 0 50 323.130102354156 73.7397952916881 {}
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A 4 -9.642857142857142 17.85714285714286 48.0818286351295 21.80140948635181 62.65738573560834 {}
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A 4 -4.6875 -11.25 41.25118369513777 269.5659493678606 74.60789655596687 {}
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T {@name} -11.25 -5 0 0 0.2 0.2 {}
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T {@#1:net_name} -20 -18.75 0 1 0.15 0.15 {layer=15}
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T {@#0:net_name} 35 1.25 0 0 0.15 0.15 {layer=15}
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T {@#2:net_name} -20 10 0 1 0.15 0.15 {layer=15}
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