better swap_windows() function (used when closing a window in multi-window(non-tabbed) interface, resolved_net() recognize global nodes. remove static data from record_global_node(), put in xctx. Remove dead code from translate() (@spice_get_voltage)
This commit is contained in:
stefan schippers
parent
8c29d0e812
commit
ecca0ba2be
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@ -1078,7 +1078,6 @@ void draw_crosshair(int del)
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int callback(const char *winpath, int event, int mx, int my, KeySym key,
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int button, int aux, int state)
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{
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static char old_winpath[PATH_MAX] = ".drw"; /* previous focused window, used to do context switch */
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char str[PATH_MAX + 100];
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struct stat buf;
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int redraw_only;
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@ -184,6 +184,7 @@ int yyparse_error = 0;
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char *xschem_executable=NULL;
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Tcl_Interp *interp = NULL;
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double *character[256]; /* array or per-char coordinates of xschem internal vector font */
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char old_winpath[PATH_MAX] = ".drw"; /* previously switched window, used in callback() */
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#ifndef __unix__
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char win_temp_dir[PATH_MAX]="";
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const char fopen_read_mode[] = "rb";
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@ -1930,6 +1930,13 @@ char *resolved_net(const char *net)
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{
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char *rnet = NULL;
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Str_hashentry *entry;
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/* global node ? return as is */
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if(net && record_global_node(3, NULL, net)) {
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my_strdup(_ALLOC_ID_, &rnet, net);
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return rnet;
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}
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if(net) {
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char *n_s1, *n_s2;
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int k, mult;
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@ -660,35 +660,36 @@ static void print_wires(void)
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/* 1: add entry */
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/* 2: delete list only, no print */
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/* 3: look if node is a global */
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int record_global_node(int what, FILE *fp, char *node)
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int record_global_node(int what, FILE *fp, const char *node)
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{
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static int max_globals=0; /* safe to keep even with multiple schematics, netlist code always resets data */
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static int size_globals=0; /* safe to keep even with multiple schematics, netlist code always resets data */
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static char **globals=NULL; /* safe to keep even with multiple schematics, netlist code always resets data */
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int i;
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if( what==1 || what==3) {
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if( what == 1 || what == 3) {
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if(!node) return 0;
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if(!strcmp(node, "0")) return 1;
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for(i=0;i<max_globals; ++i) {
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if( !strcmp(node, globals[i] )) return 1; /* node is a global */
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for(i = 0;i < xctx->max_globals; ++i) {
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if( !strcmp(node, xctx->globals[i] )) return 1; /* node is a global */
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}
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if(what == 3) return 0; /* node is not a global */
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if(max_globals>=size_globals) {
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size_globals+=CADCHUNKALLOC;
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my_realloc(_ALLOC_ID_, &globals, size_globals*sizeof(char *) );
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if(xctx->max_globals >= xctx->size_globals) {
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xctx->size_globals+=CADCHUNKALLOC;
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my_realloc(_ALLOC_ID_, &xctx->globals, xctx->size_globals*sizeof(char *) );
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}
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globals[max_globals]=NULL;
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my_strdup(_ALLOC_ID_, &globals[max_globals], node);
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max_globals++;
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} else if(what == 0 || what == 2) {
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for(i=0;i<max_globals; ++i) {
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if(what == 0 && xctx->netlist_type == CAD_SPICE_NETLIST) fprintf(fp, ".GLOBAL %s\n", globals[i]);
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if(what == 0 && xctx->netlist_type == CAD_TEDAX_NETLIST) fprintf(fp, "__GLOBAL__ %s\n", globals[i]);
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my_free(_ALLOC_ID_, &globals[i]);
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xctx->globals[xctx->max_globals]=NULL;
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my_strdup(_ALLOC_ID_, &xctx->globals[xctx->max_globals], node);
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xctx->max_globals++;
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} else if(what == 0) {
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for(i = 0;i < xctx->max_globals; ++i) {
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if(xctx->netlist_type == CAD_SPICE_NETLIST) fprintf(fp, ".GLOBAL %s\n", xctx->globals[i]);
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if(xctx->netlist_type == CAD_TEDAX_NETLIST) fprintf(fp, "__GLOBAL__ %s\n", xctx->globals[i]);
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}
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my_free(_ALLOC_ID_, &globals);
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size_globals=max_globals=0;
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} else if(what == 2) {
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for(i=0;i<xctx->max_globals; ++i) {
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my_free(_ALLOC_ID_, &xctx->globals[i]);
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}
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my_free(_ALLOC_ID_, &xctx->globals);
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xctx->size_globals = xctx->max_globals=0;
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}
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return 0;
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}
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@ -803,9 +803,10 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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": UNSAVED data: want to exit?\"");
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}
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if(force || !xctx->modified || !strcmp(tclresult(), "ok")) {
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swap_windows();
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swap_windows(0);
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set_modify(0); /* set modified status to 0 to avoid another confirm in following line */
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new_schematic("destroy", xctx->current_win_path, NULL, 1);
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new_schematic("destroy", xctx->current_win_path, NULL, 0);
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draw();
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}
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} else {
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if(!force && xctx->modified) {
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@ -1624,8 +1625,6 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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my_snprintf(res, S(res), "sch[%d]=%s\n",i,xctx->sch[i]); Tcl_AppendResult(interp, res, NULL);
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}
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my_snprintf(res, S(res), "modified=%d\n", xctx->modified); Tcl_AppendResult(interp, res, NULL);
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my_snprintf(res, S(res), "areaw=%d\n", xctx->areaw); Tcl_AppendResult(interp, res, NULL);
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my_snprintf(res, S(res), "areah=%d\n", xctx->areah); Tcl_AppendResult(interp, res, NULL);
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my_snprintf(res, S(res), "color_ps=%d\n", color_ps); Tcl_AppendResult(interp, res, NULL);
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my_snprintf(res, S(res), "hilight_nets=%d\n", xctx->hilight_nets); Tcl_AppendResult(interp, res, NULL);
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my_snprintf(res, S(res), "semaphore=%d\n", xctx->semaphore); Tcl_AppendResult(interp, res, NULL);
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@ -3354,6 +3353,22 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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rebuild_selected_array();
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}
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/* record_global_node n node
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call the record_global_node function (list of netlist global nodes) */
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else if(!strcmp(argv[1], "record_global_node"))
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{
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int ret = 0;
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if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
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if(argc > 2) {
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int n = atoi(argv[2]);
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if(n == 1 && argc > 3) ret = record_global_node(1,NULL, argv[3]); /* insert node */
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else if(n == 0) ret = record_global_node(0, stdout, NULL);
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else if(n == 2) ret = record_global_node(2, NULL, NULL);
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else if(n == 3 && argc > 3) ret = record_global_node(3, NULL, argv[3]); /* look up node */
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}
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Tcl_SetResult(interp, my_itoa(ret), TCL_VOLATILE);
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}
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/* rect [x1 y1 x2 y2] [pos] [propstring] [draw]
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* if 'x1 y1 x2 y2'is given place recangle on current
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* layer (rectcolor) at indicated coordinates.
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@ -4544,6 +4559,17 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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Tcl_ResetResult(interp);
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}
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/* swap_windows
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* swap first and second window in window interface (internal command)
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*/
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else if(!strcmp(argv[1], "swap_windows"))
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{
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if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
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if(!tclgetboolvar("tabbed_interface") && get_window_count()) {
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swap_windows(1);
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}
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}
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/* switch [window_path |schematic_name]
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* Switch context to indicated window path or schematic name
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* returns 0 if switch was successfull or 1 in case of errors
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@ -461,7 +461,10 @@ int global_spice_netlist(int global) /* netlister driver */
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my_free(_ALLOC_ID_, &stored_flags);
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/* print globals nodes found in netlist 28032003 */
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if(!split_f) record_global_node(0,fd,NULL);
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if(!split_f) {
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record_global_node(0,fd,NULL);
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/* record_global_node(2, NULL, NULL); */ /* delete list --> do it in xwin_exit() */
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}
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/* =================================== 20121223 */
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first = 0;
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@ -259,6 +259,7 @@ int global_tedax_netlist(int global) /* netlister driver */
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/* print globals nodes found in netlist 28032003 */
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record_global_node(0,fd,NULL);
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/* record_global_node(2, NULL, NULL); */ /* delete list --> do it in xwin_exit() */
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fprintf(fd, "__HIERSEP__ %s\n", xctx->hiersep);
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dbg(1, "global_tedax_netlist(): starting awk on netlist!\n");
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20
src/token.c
20
src/token.c
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@ -3605,12 +3605,7 @@ const char *translate(int inst, const char* s)
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double val;
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const char *valstr;
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if(path) {
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int skip = 0;
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/* skip path components that are above the level where raw file was loaded */
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while(*path && skip < start_level) {
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if(*path == '.') skip++;
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++path;
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}
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prepare_netlist_structs(0);
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if(xctx->inst[inst].lab) {
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my_strdup2(_ALLOC_ID_, &net, expandlabel(xctx->inst[inst].lab, &multip));
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@ -3618,16 +3613,10 @@ const char *translate(int inst, const char* s)
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if(net == NULL || net[0] == '\0') {
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my_strdup2(_ALLOC_ID_, &net, net_name(inst, 0, &multip, 0, 0));
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}
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if(multip == 1 && net && net[0] && path) {
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if(multip == 1 && net && net[0]) {
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char *rn;
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len = strlen(path) + strlen(net) + 1;
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dbg(1, "translate() @spice_get_voltage: inst=%s\n", instname);
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dbg(1, " net=%s\n", net);
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/*
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* fqnet = my_malloc(_ALLOC_ID_, len);
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* my_snprintf(fqnet, len, "%s%s", path, net);
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*/
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rn = resolved_net(net);
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if(rn) {
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my_strdup2(_ALLOC_ID_, &fqnet, rn);
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@ -3685,11 +3674,16 @@ const char *translate(int inst, const char* s)
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n = sscanf(token + 19, "%[^)]", net);
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expandlabel(net, &multip);
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if(n == 1 && multip == 1) {
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strtolower(net);
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len = strlen(path) + strlen(instname) + strlen(net) + 2;
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dbg(1, "net=%s\n", net);
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fqnet = my_malloc(_ALLOC_ID_, len);
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if(record_global_node(3, NULL, net)) {
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strtolower(net);
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my_snprintf(fqnet, len, "%s", net);
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} else {
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strtolower(net);
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my_snprintf(fqnet, len, "%s%s.%s", path, instname, net);
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}
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strtolower(fqnet);
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dbg(1, "translate(): net=%s, fqnet=%s start_level=%d\n", net, fqnet, start_level);
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idx = get_raw_index(fqnet);
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51
src/xinit.c
51
src/xinit.c
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@ -619,6 +619,9 @@ static void alloc_xschem_data(const char *top_path, const char *win_path)
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xctx->save_lw = 0.0; /* used to save linewidth when selecting 'only_probes' view */
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xctx->already_selected = 0;
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xctx->onetime = 0; /* callback() static var */
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xctx->max_globals = 0;
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xctx->size_globals = 0;
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xctx->globals = NULL;
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xctx->save_netlist_type = 0;
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xctx->some_nets_added = 0;
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xctx->loaded_symbol = 0;
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@ -680,6 +683,7 @@ static void delete_schematic_data(int delete_pixmap)
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extra_rawfile(3, NULL, NULL);
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free_rawfile(&xctx->raw, 0);
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statusmsg("", 1); /* clear allocated string */
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record_global_node(2, NULL, NULL); /* delete global node array */
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free_xschem_data(); /* delete the xctx struct */
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}
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@ -910,7 +914,6 @@ static void xwin_exit(void)
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dbg(1, "xwin_exit(): closed display\n");
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my_strncpy(cli_opt_filename, "", S(cli_opt_filename));
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my_free(_ALLOC_ID_, &xschem_executable);
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record_global_node(2, NULL, NULL); /* delete global node array */
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dbg(1, "xwin_exit(): deleted undo buffer\n");
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/* delete cmdline stuff */
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for(i = 0 ; i < cli_opt_argc; ++i) {
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@ -1276,9 +1279,11 @@ void swap_tabs(void)
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}
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}
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/* swap primary view (.drw) with first valid tab (x1.drw, x2.drw, ...)
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* used for window close ('xschem exit' command) */
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void swap_windows(void)
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/* swap primary view (.drw) with first valid window (x1.drw, x2.drw, ...)
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* used for window close ('xschem exit' command)
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* if dr == 1 do draw and don't move following window onto first. This is used if
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* primary windows is about to be deleted */
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void swap_windows(int dr)
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{
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int wc = window_count;
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if(tclgetboolvar("tabbed_interface")) return;
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@ -1287,10 +1292,7 @@ void swap_windows(void)
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char *tmp;
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char wp_i[WINDOW_PATH_SIZE], wp_j[WINDOW_PATH_SIZE];
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Window window;
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Pixmap save_pixmap;
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GC gc, *gcptr;
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int i = 0;
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int j;
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int i = 0, j;
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Tk_Window tkwin, mainwindow;
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char geometry[80];
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@ -1336,34 +1338,23 @@ void swap_windows(void)
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save_xctx[i] = save_xctx[j];
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save_xctx[j] = ctx;
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/* swap window paths */
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/* re-swap window paths */
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SWAP(save_xctx[i]->top_path, save_xctx[j]->top_path, tmp);
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SWAP(save_xctx[i]->current_win_path, save_xctx[j]->current_win_path, tmp);
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/* swap drawing stuff */
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SWAP(save_xctx[i]->save_pixmap, save_xctx[j]->save_pixmap, save_pixmap);
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/* re-swap window IDs */
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SWAP(save_xctx[i]->window, save_xctx[j]->window, window);
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SWAP(save_xctx[i]->gctiled, save_xctx[j]->gctiled, gc);
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SWAP(save_xctx[i]->gc, save_xctx[j]->gc, gcptr);
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SWAP(save_xctx[i]->gcstipple, save_xctx[j]->gcstipple, gcptr);
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/* rebuld colors and pixmaps, redraw swapped schematics */
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tclvareval("restore_ctx ", wp_i, NULL);
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new_schematic("switch", wp_i, "", 1);
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tclvareval("housekeeping_ctx", NULL);
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tclvareval("xschem build_colors", NULL);
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resetwin(1, 1, 1, 0, 0);
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new_schematic("switch", wp_i, "", 0);
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/* move primary window to location of deleted window */
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tclvareval("wm geometry . ", geometry, NULL);
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draw();
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/* set context to window that is about to be deleted */
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tclvareval("restore_ctx ", wp_j, NULL);
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new_schematic("switch", wp_j, "", 1);
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tclvareval("housekeeping_ctx", NULL);
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tclvareval("xschem build_colors", NULL);
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if(!dr) tclvareval("wm geometry . ", geometry, "; update", NULL);
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resetwin(1, 1, 1, 0, 0);
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/* draw(); */ /* avoid drawing, since usually this will be destroyed soon after */
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if(dr) draw();
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new_schematic("switch", wp_j, "", 0);
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resetwin(1, 1, 1, 0, 0);
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my_snprintf(old_winpath, S(old_winpath), "");
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if(dr) draw();
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}
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}
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@ -1030,6 +1030,10 @@ typedef struct {
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int mx_s, my_s;
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int mmx_s, mmy_s;
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double xorig_save, yorig_save;
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/* record_global_node() */
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int max_globals;
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int size_globals;
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char **globals;
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/* load_schematic */
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int save_netlist_type;
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int loaded_symbol;
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@ -1174,6 +1178,7 @@ extern int yyparse_error;
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extern char *xschem_executable;
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extern Tcl_Interp *interp;
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extern double *character[256];
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extern char old_winpath[PATH_MAX]; /* previously switched window, used in callback() */
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extern const char fopen_read_mode[]; /* "r" on unix, "rb" on windows */
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/*********** Cmdline options (used at xinit, and then not used anymore) ***********/
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@ -1451,7 +1456,7 @@ extern void mem_clear_undo(void);
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extern void load_schematic(int load_symbol, const char *fname, int reset_undo, int alert);
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/* check if filename already in an open window/tab */
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extern void swap_tabs(void);
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extern void swap_windows(void);
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extern void swap_windows(int dr);
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extern int check_loaded(const char *f, char *win_path);
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extern char *get_window_path(int i);
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extern int get_window_count(void);
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@ -1615,7 +1620,7 @@ extern void select_arc(int c, int i, unsigned short select_mode, int fast);
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extern void select_line(int c, int i, unsigned short select_mode, int fast);
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extern void select_polygon(int c, int i, unsigned short select_mode, int fast );
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extern const char *net_name(int i, int j, int *mult, int hash_prefix_unnamed_net, int erc);
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extern int record_global_node(int what, FILE *fp, char *node);
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extern int record_global_node(int what, FILE *fp, const char *node);
|
||||
extern int count_items(const char *s, const char *sep, const char *quote);
|
||||
extern int get_unnamed_node(int what, int mult, int node);
|
||||
extern void node_hash_free(void);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
v {xschem version=3.4.4 file_version=1.2
|
||||
v {xschem version=3.4.5 file_version=1.2
|
||||
*
|
||||
* This file is part of XSCHEM,
|
||||
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
|
||||
|
|
@ -32,3 +32,4 @@ L 4 0 -20 0 0 {}
|
|||
L 4 -10 -20 10 -20 {}
|
||||
B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout verilog_type=wire goto=0}
|
||||
T {@lab} -12.5 -35 0 0 0.2 0.2 {}
|
||||
T {@spice_get_voltage} 6.875 -16.09375 0 0 0.2 0.2 {layer=15}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
v {xschem version=3.4.4 file_version=1.2
|
||||
v {xschem version=3.4.5 file_version=1.2
|
||||
*
|
||||
* This file is part of XSCHEM,
|
||||
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
|
||||
|
|
@ -32,13 +32,11 @@ N 370 -180 550 -180 { lab=GN1}
|
|||
N 330 -230 330 -210 { lab=GN1}
|
||||
N 330 -310 330 -290 { lab=VCC}
|
||||
N 330 -150 330 -130 { lab=0}
|
||||
N 510 -240 670 -240 { lab=#net1}
|
||||
N 590 -240 670 -240 { lab=#net1}
|
||||
N 590 -240 590 -210 { lab=#net1}
|
||||
N 510 -340 510 -300 { lab=#net2}
|
||||
N 670 -340 670 -300 { lab=#net3}
|
||||
N 550 -410 550 -380 { lab=#net2}
|
||||
N 510 -380 550 -380 { lab=#net2}
|
||||
N 510 -380 510 -340 { lab=#net2}
|
||||
N 510 -380 510 -300 { lab=#net2}
|
||||
N 510 -460 510 -440 { lab=VCC}
|
||||
N 800 -460 800 -400 { lab=VCC}
|
||||
N 670 -370 760 -370 { lab=#net3}
|
||||
|
|
@ -47,35 +45,56 @@ N 370 -210 370 -180 { lab=GN1}
|
|||
N 670 -460 670 -440 { lab=VCC}
|
||||
N 550 -410 640 -410 { lab=#net2}
|
||||
N 800 -150 800 -130 { lab=0}
|
||||
N 800 -340 800 -210 { lab=#net4}
|
||||
N 800 -290 800 -210 { lab=#net4}
|
||||
N 550 -180 550 -170 { lab=GN1}
|
||||
N 550 -170 660 -170 { lab=GN1}
|
||||
N 660 -180 660 -170 { lab=GN1}
|
||||
N 660 -180 760 -180 { lab=GN1}
|
||||
N 670 -380 670 -340 { lab=#net3}
|
||||
N 1130 -290 1170 -290 { lab=OUT}
|
||||
N 800 -290 870 -290 { lab=#net4}
|
||||
N 670 -370 670 -300 { lab=#net3}
|
||||
N 1160 -290 1200 -290 { lab=OUT}
|
||||
N 800 -290 890 -290 { lab=#net4}
|
||||
N 980 -150 980 -130 { lab=0}
|
||||
N 980 -420 980 -400 { lab=VCC}
|
||||
N 940 -370 940 -180 { lab=#net4}
|
||||
N 980 -340 980 -210 { lab=#net5}
|
||||
N 870 -290 940 -290 { lab=#net4}
|
||||
N 1130 -150 1130 -130 { lab=0}
|
||||
N 1130 -420 1130 -400 { lab=VCC}
|
||||
N 1090 -370 1090 -180 { lab=#net5}
|
||||
N 1130 -340 1130 -210 { lab=OUT}
|
||||
N 980 -290 1090 -290 { lab=#net5}
|
||||
N 990 -620 990 -510 { lab=#net5}
|
||||
N 930 -620 930 -510 { lab=#net4}
|
||||
N 940 -290 940 -180 { lab=#net4}
|
||||
N 980 -290 980 -210 { lab=#net5}
|
||||
N 890 -290 940 -290 { lab=#net4}
|
||||
N 1160 -150 1160 -130 { lab=0}
|
||||
N 1160 -420 1160 -400 { lab=VCC}
|
||||
N 1120 -290 1120 -180 { lab=#net5}
|
||||
N 1160 -290 1160 -210 { lab=OUT}
|
||||
N 1060 -290 1120 -290 { lab=#net5}
|
||||
N 990 -560 990 -510 { lab=#net5}
|
||||
N 930 -560 930 -470 { lab=#net4}
|
||||
N 890 -560 930 -560 { lab=#net4}
|
||||
N 890 -560 890 -290 { lab=#net4}
|
||||
N 990 -560 1010 -560 { lab=#net5}
|
||||
N 1010 -560 1030 -560 { lab=#net5}
|
||||
N 1030 -560 1030 -290 { lab=#net5}
|
||||
N 1060 -560 1060 -290 { lab=#net5}
|
||||
N 960 -660 990 -660 { lab=#net5}
|
||||
N 990 -660 990 -620 { lab=#net5}
|
||||
N 930 -510 930 -470 { lab=#net4}
|
||||
N 990 -660 990 -560 { lab=#net5}
|
||||
N 930 -470 960 -470 { lab=#net4}
|
||||
N 710 -270 740 -270 {
|
||||
lab=PLUS}
|
||||
N 440 -270 470 -270 {
|
||||
lab=MINUS}
|
||||
N 670 -410 700 -410 {
|
||||
lab=VCC}
|
||||
N 480 -410 510 -410 {
|
||||
lab=VCC}
|
||||
N 800 -370 830 -370 {
|
||||
lab=VCC}
|
||||
N 980 -370 1010 -370 {
|
||||
lab=VCC}
|
||||
N 510 -240 590 -240 { lab=#net1}
|
||||
N 670 -380 670 -370 { lab=#net3}
|
||||
N 1160 -340 1160 -290 { lab=OUT}
|
||||
N 800 -340 800 -290 { lab=#net4}
|
||||
N 940 -370 940 -290 { lab=#net4}
|
||||
N 980 -340 980 -290 { lab=#net5}
|
||||
N 1120 -370 1120 -290 { lab=#net5}
|
||||
N 930 -620 930 -560 { lab=#net4}
|
||||
N 980 -290 1060 -290 { lab=#net5}
|
||||
N 990 -560 1060 -560 { lab=#net5}
|
||||
N 1160 -370 1190 -370 {
|
||||
lab=VCC}
|
||||
C {nmos4.sym} 570 -180 0 0 {name=M1 model=nmos w=4u l=0.4u m=1}
|
||||
C {lab_pin.sym} 590 -180 0 1 {name=p2 lab=0}
|
||||
C {lab_pin.sym} 590 -130 0 0 {name=p6 lab=0}
|
||||
|
|
@ -91,18 +110,18 @@ C {lab_pin.sym} 670 -270 0 0 {name=p18 lab=0 l=0.2u}
|
|||
C {pmos4.sym} 530 -410 0 1 {name=M5 model=pmos w=6u l=0.3u m=1}
|
||||
C {pmos4.sym} 650 -410 0 0 {name=M6 model=pmos w=6u l=0.3u m=1}
|
||||
C {lab_pin.sym} 670 -460 0 0 {name=p21 lab=VCC}
|
||||
C {lab_pin.sym} 510 -410 0 0 {name=p23 lab=VCC}
|
||||
C {lab_pin.sym} 670 -410 0 1 {name=p33 lab=VCC}
|
||||
C {lab_pin.sym} 480 -410 0 0 {name=p23 lab=VCC}
|
||||
C {lab_pin.sym} 700 -410 0 1 {name=p33 lab=VCC}
|
||||
C {lab_wire.sym} 500 -180 0 0 {name=l2 lab=GN1}
|
||||
C {ipin.sym} 100 -310 0 0 {name=p161 lab=PLUS}
|
||||
C {ipin.sym} 100 -260 0 0 {name=p1 lab=MINUS}
|
||||
C {opin.sym} 180 -290 0 0 {name=p20 lab=OUT}
|
||||
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
|
||||
C {lab_pin.sym} 710 -270 0 1 {name=p3 lab=PLUS}
|
||||
C {lab_pin.sym} 470 -270 0 0 {name=p4 lab=MINUS}
|
||||
C {lab_pin.sym} 1170 -290 0 1 {name=p14 lab=OUT}
|
||||
C {lab_pin.sym} 740 -270 0 1 {name=p3 lab=PLUS}
|
||||
C {lab_pin.sym} 440 -270 0 0 {name=p4 lab=MINUS}
|
||||
C {lab_pin.sym} 1200 -290 0 1 {name=p14 lab=OUT}
|
||||
C {pmos4.sym} 780 -370 0 0 {name=M14 model=pmos w=6u l=0.3u m=1}
|
||||
C {lab_pin.sym} 800 -370 0 1 {name=p15 lab=VCC}
|
||||
C {lab_pin.sym} 830 -370 0 1 {name=p15 lab=VCC}
|
||||
C {lab_pin.sym} 800 -460 0 0 {name=p22 lab=VCC}
|
||||
C {spice_probe.sym} 420 -180 0 0 {name=p27 attrs=""}
|
||||
C {spice_probe.sym} 570 -410 0 0 {name=p28 attrs=""}
|
||||
|
|
@ -113,17 +132,17 @@ C {nmos4.sym} 960 -180 0 0 {name=M8 model=nmos w=1u l=0.4u m=1}
|
|||
C {lab_pin.sym} 980 -180 0 1 {name=p10 lab=0}
|
||||
C {lab_pin.sym} 980 -130 0 1 {name=p11 lab=0}
|
||||
C {pmos4.sym} 960 -370 0 0 {name=M9 model=pmos w=2u l=0.4u m=1}
|
||||
C {lab_pin.sym} 980 -370 0 1 {name=p12 lab=VCC}
|
||||
C {lab_pin.sym} 1010 -370 0 1 {name=p12 lab=VCC}
|
||||
C {lab_pin.sym} 980 -420 0 0 {name=p13 lab=VCC}
|
||||
C {nmos4.sym} 1110 -180 0 0 {name=M10 model=nmos w=1u l=0.4u m=1}
|
||||
C {lab_pin.sym} 1130 -180 0 1 {name=p24 lab=0}
|
||||
C {lab_pin.sym} 1130 -130 0 1 {name=p25 lab=0}
|
||||
C {pmos4.sym} 1110 -370 0 0 {name=M11 model=pmos w=2u l=0.4u m=1}
|
||||
C {lab_pin.sym} 1130 -370 0 1 {name=p26 lab=VCC}
|
||||
C {lab_pin.sym} 1130 -420 0 0 {name=p29 lab=VCC}
|
||||
C {nmos4.sym} 1140 -180 0 0 {name=M10 model=nmos w=1u l=0.4u m=1}
|
||||
C {lab_pin.sym} 1160 -180 0 1 {name=p24 lab=0}
|
||||
C {lab_pin.sym} 1160 -130 0 1 {name=p25 lab=0}
|
||||
C {pmos4.sym} 1140 -370 0 0 {name=M11 model=pmos w=2u l=0.4u m=1}
|
||||
C {lab_pin.sym} 1190 -370 0 1 {name=p26 lab=VCC}
|
||||
C {lab_pin.sym} 1160 -420 0 0 {name=p29 lab=VCC}
|
||||
C {nmos4.sym} 960 -490 3 0 {name=M13 model=nmos w=2u l=0.1u m=1}
|
||||
C {lab_pin.sym} 960 -510 3 1 {name=p31 lab=0}
|
||||
C {spice_probe.sym} 1040 -290 0 0 {name=p35 attrs=""}
|
||||
C {spice_probe.sym} 1070 -290 0 0 {name=p35 attrs=""}
|
||||
C {spice_probe.sym} 840 -290 0 0 {name=p36 attrs=""}
|
||||
C {nmos4.sym} 960 -640 1 0 {name=M12 model=nmos w=2u l=0.1u m=1}
|
||||
C {lab_pin.sym} 960 -620 1 1 {name=p30 lab=0}
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ unitx=n
|
|||
divy=2
|
||||
digital=1}
|
||||
P 4 5 700 -480 1680 -480 1680 -90 700 -90 700 -480 {dash=5}
|
||||
P 5 5 40 -670 970 -670 970 -230 40 -230 40 -670 { dash=5}
|
||||
P 5 5 40 -670 690 -670 690 -230 40 -230 40 -670 { dash=5}
|
||||
T {Modulator} 530 -710 0 0 0.6 0.6 { layer=5}
|
||||
T {Digital Decimator} 1030 -520 0 0 0.6 0.6 {layer=4}
|
||||
T {D} 190 -530 0 0 1 1 { layer=5 font=Symbol}
|
||||
|
|
@ -169,3 +169,7 @@ C {opamp_65nm.sym} 380 -400 2 1 {name=x41}
|
|||
C {comp_65nm.sym} 610 -410 0 0 {name=x42}
|
||||
C {spice_probe.sym} 1470 -430 0 0 {name=p2 attrs=""}
|
||||
C {or_ngspice.sym} 1110 -320 0 0 {name=x3 ROUT=1000 net_name=true}
|
||||
C {opamp_65nm.sch} -180 -650 0 0 {name=x10}
|
||||
C {lab_pin.sym} 100 -930 0 0 {name=p7 lab=FB}
|
||||
C {lab_pin.sym} 890 -980 0 1 {name=p9 lab=OUT}
|
||||
C {lab_pin.sym} 100 -1070 0 0 {name=p13 lab=VREF}
|
||||
|
|
|
|||
|
|
@ -111,8 +111,11 @@ value="
|
|||
.measure tran avg2 AVG v(x1.qn) from=4u to=6u
|
||||
.measure tran avg3 AVG v(x1.qn) from=7u to=9u
|
||||
.control
|
||||
* save all
|
||||
tran 0.2n 9u uic
|
||||
tran 0.2n .9u uic
|
||||
write delta_sigma.raw
|
||||
set appendwrite
|
||||
save all
|
||||
op
|
||||
write delta_sigma.raw
|
||||
quit 0
|
||||
.endc
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
v {xschem version=3.4.4 file_version=1.2
|
||||
v {xschem version=3.4.5 file_version=1.2
|
||||
*
|
||||
* This file is part of XSCHEM,
|
||||
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
|
||||
|
|
@ -20,41 +20,47 @@ v {xschem version=3.4.4 file_version=1.2
|
|||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
K {type=subcircuit
|
||||
format="@name @pinlist @symname"
|
||||
template="name=x1"
|
||||
}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
T {( @#0:resolved_net )} 100 -335 0 1 0.2 0.2 {name=p161 layer=15}
|
||||
T {( @#0:resolved_net )} 100 -285 0 1 0.2 0.2 {name=p1 layer=15}
|
||||
T {( @#0:resolved_net )} 240 -315 0 1 0.2 0.2 {name=p20 layer=15}
|
||||
P 4 5 280 -580 1070 -580 1070 -130 280 -130 280 -580 {dash=3}
|
||||
T {( @#0:resolved_net )} 280 -445 0 1 0.2 0.2 {name=p161 layer=15}
|
||||
T {( @#0:resolved_net )} 280 -305 0 1 0.2 0.2 {name=p1 layer=15}
|
||||
T {( @#0:resolved_net )} 1130 -355 0 1 0.2 0.2 {name=p20 layer=15}
|
||||
T {@name} 320 -640 0 0 0.8 0.8 {}
|
||||
T {@symname} 1000 -640 0 1 0.8 0.8 {}
|
||||
N 660 -190 660 -170 { lab=0}
|
||||
N 440 -220 620 -220 { lab=GN1}
|
||||
N 400 -270 400 -250 { lab=GN1}
|
||||
N 400 -350 400 -330 { lab=VCC}
|
||||
N 400 -190 400 -170 { lab=0}
|
||||
N 580 -280 740 -280 { lab=#net1}
|
||||
N 660 -280 660 -250 { lab=#net1}
|
||||
N 580 -380 580 -340 { lab=#net2}
|
||||
N 740 -380 740 -340 { lab=#net3}
|
||||
N 620 -450 620 -420 { lab=#net2}
|
||||
N 580 -420 620 -420 { lab=#net2}
|
||||
N 580 -420 580 -380 { lab=#net2}
|
||||
N 580 -280 740 -280 { lab=S}
|
||||
N 660 -280 660 -250 { lab=S}
|
||||
N 580 -380 580 -340 { lab=#net1}
|
||||
N 740 -380 740 -340 { lab=G}
|
||||
N 620 -450 620 -420 { lab=#net1}
|
||||
N 580 -420 620 -420 { lab=#net1}
|
||||
N 580 -420 580 -380 { lab=#net1}
|
||||
N 580 -500 580 -480 { lab=VCC}
|
||||
N 940 -330 1060 -330 { lab=OUT}
|
||||
N 940 -330 1070 -330 { lab=OUT}
|
||||
N 940 -500 940 -440 { lab=VCC}
|
||||
N 740 -410 900 -410 { lab=#net3}
|
||||
N 740 -410 900 -410 { lab=G}
|
||||
N 400 -250 440 -250 { lab=GN1}
|
||||
N 440 -250 440 -220 { lab=GN1}
|
||||
N 740 -500 740 -480 { lab=VCC}
|
||||
N 620 -450 710 -450 { lab=#net2}
|
||||
N 620 -450 710 -450 { lab=#net1}
|
||||
N 940 -190 940 -170 { lab=0}
|
||||
N 940 -380 940 -250 { lab=OUT}
|
||||
N 620 -220 620 -210 { lab=GN1}
|
||||
N 620 -210 730 -210 { lab=GN1}
|
||||
N 730 -220 730 -210 { lab=GN1}
|
||||
N 730 -220 900 -220 { lab=GN1}
|
||||
N 740 -420 740 -380 { lab=#net3}
|
||||
N 790 -410 790 -340 { lab=#net3}
|
||||
N 740 -420 740 -380 { lab=G}
|
||||
N 790 -410 790 -340 { lab=G}
|
||||
N 910 -340 940 -340 { lab=OUT}
|
||||
C {nmos4.sym} 640 -220 0 0 {name=M1 model=nmos w=4u l=0.4u m=1}
|
||||
C {lab_pin.sym} 660 -220 0 1 {name=p2 lab=0}
|
||||
|
|
@ -67,7 +73,7 @@ C {lab_pin.sym} 400 -170 0 0 {name=p16 lab=0}
|
|||
C {nmos4.sym} 560 -310 0 0 {name=M3 model=nmos w=1.5u l=0.2u m=1}
|
||||
C {lab_pin.sym} 580 -310 0 1 {name=p17 lab=0}
|
||||
C {nmos4.sym} 760 -310 0 1 {name=M4 model=nmos w=1.5u l=0.2u m=1}
|
||||
C {lab_pin.sym} 740 -310 0 0 {name=p18 lab=0 l=0.2u}
|
||||
C {lab_pin.sym} 740 -310 0 0 {name=p18 lab=0}
|
||||
C {pmos4.sym} 600 -450 0 1 {name=M5 model=pmos w=6u l=0.3u m=1}
|
||||
C {lab_pin.sym} 580 -500 0 0 {name=p19 lab=VCC}
|
||||
C {pmos4.sym} 720 -450 0 0 {name=M6 model=pmos w=6u l=0.3u m=1}
|
||||
|
|
@ -75,13 +81,12 @@ C {lab_pin.sym} 740 -500 0 0 {name=p21 lab=VCC}
|
|||
C {lab_pin.sym} 580 -450 0 0 {name=p23 lab=VCC}
|
||||
C {lab_pin.sym} 740 -450 0 1 {name=p33 lab=VCC}
|
||||
C {lab_wire.sym} 570 -220 0 0 {name=l2 lab=GN1}
|
||||
C {ipin.sym} 100 -310 0 0 {name=p161 lab=PLUS}
|
||||
C {ipin.sym} 100 -260 0 0 {name=p1 lab=MINUS}
|
||||
C {opin.sym} 180 -290 0 0 {name=p20 lab=OUT}
|
||||
C {ipin.sym} 280 -420 0 0 {name=p161 lab=PLUS}
|
||||
C {ipin.sym} 280 -280 0 0 {name=p1 lab=MINUS}
|
||||
C {opin.sym} 1070 -330 0 0 {name=p20 lab=OUT}
|
||||
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
|
||||
C {lab_pin.sym} 780 -310 0 1 {name=p3 lab=PLUS}
|
||||
C {lab_pin.sym} 540 -310 0 0 {name=p4 lab=MINUS}
|
||||
C {lab_pin.sym} 1060 -330 0 1 {name=p14 lab=OUT}
|
||||
C {pmos4.sym} 920 -410 0 0 {name=M8 model=pmos w=6u l=0.4u m=1}
|
||||
C {lab_pin.sym} 940 -410 0 1 {name=p15 lab=VCC}
|
||||
C {lab_pin.sym} 940 -500 0 0 {name=p22 lab=VCC}
|
||||
|
|
@ -102,3 +107,5 @@ footprint=1206
|
|||
device="ceramic capacitor"}
|
||||
C {parax_cap.sym} 460 -210 0 0 {name=C2 gnd=0 value=200f m=1}
|
||||
C {spice_probe.sym} 630 -280 0 0 {name=p10 attrs=""}
|
||||
C {lab_pin.sym} 660 -260 0 0 {name=p11 lab=S}
|
||||
C {lab_pin.sym} 740 -380 0 0 {name=p12 lab=G}
|
||||
|
|
|
|||
Loading…
Reference in New Issue