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xschem
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has_included_subcircuit() and proc has_included_subcircuit: compare and reorder only ports with associated symbol pin. do not consider `extra` ports assigned via attributes

This commit is contained in:
stefan schippers 2025-01-03 00:49:54 +01:00
parent 294a10bd5a
commit e77cc334f4
2 changed files with 15 additions and 7 deletions
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5
src/token.c
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@ -1848,6 +1848,7 @@ static int has_included_subcircuit(int inst, int symbol, char **result)
char *symname = NULL;
char *templ = NULL;
char *symname_attr = NULL;
int no_of_pins = (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER];
my_strdup2(_ALLOC_ID_, &templ, get_tok_value(xctx->sym[symbol].prop_ptr, "template", 0));
my_strdup2(_ALLOC_ID_, &symname, get_tok_value(xctx->inst[inst].prop_ptr, "schematic", 0));
@ -1866,7 +1867,7 @@ static int has_included_subcircuit(int inst, int symbol, char **result)
dbg(1, "has_included_subcircuit(): symname=%s\n", symname);
strtolower(symname);
tclvareval("has_included_subcircuit {", get_cell(symname, 0), "} {",
translated_sym_def, "}", NULL);
translated_sym_def, "} ", my_itoa(no_of_pins), NULL);
my_free(_ALLOC_ID_, &templ);
my_free(_ALLOC_ID_, &symname_attr);
if(tclresult()[0]) {
@ -1875,7 +1876,7 @@ static int has_included_subcircuit(int inst, int symbol, char **result)
char *subckt_pinlist_ptr;
char *subckt_pinlist = NULL;
char *tmp_result = NULL;
int i, no_of_pins = (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER];
int i;
int symbol_pins = 0;
int instance_pins = 0;
Str_hashentry *entry;

17
src/xschem.tcl
View File

@ -813,7 +813,7 @@ proc tabulate {text {sep ",\t "}} {
# get pin ordering from included subcircuit
# return empty string if not found.
proc has_included_subcircuit {symname spice_sym_def} {
proc has_included_subcircuit {symname spice_sym_def no_of_pins} {
global has_x
set include_found 0
regsub -all {\n\+} $spice_sym_def { } spice_sym_def
@ -853,6 +853,13 @@ proc has_included_subcircuit {symname spice_sym_def} {
} else {
set last [expr {$last -1}]
}
# if spice_sym_def has more ports than symbol (no_of_pins) assume these are extra ports
# assigned via attributes ('extra' symbol attribute, usually power rails), these extra
# ports are not returned as @pinlist and correspondence with symbol format string
# is not checked. user must ensure these additional ports are in the right order.
if { $last >= $no_of_pins + 1 } {
set last [expr {$no_of_pins + 1}]
}
set pinlist [lrange $line 2 $last]
break
}
@ -1766,7 +1773,7 @@ proc simconf_add {tool} {
proc cellview_setlabels {w sch} {
if {[$w get] ne $sch} {
if { [file exists [abs_sym_path [$w get]]] } {
$w configure -bg PaleGreen
$w configure -bg green
} else {
# puts "$sch --- [$sf.f$i.s get]"
$w configure -bg red
@ -1823,7 +1830,7 @@ proc cellview {} {
if {![file exists $abs_sch]} {
$sf.f$i.s configure -bg red
} elseif {$default_sch ne $sch} {
$sf.f$i.s configure -bg PaleGreen
$sf.f$i.s configure -bg green
}
} else {
$sf.f$i.s configure -fg red
@ -1900,14 +1907,14 @@ proc traversal_setlabels {w parent_sch sch instname default_sch inst_spice_sym_d
if {[$w get] ne $default_sch} {
if { $sym_spice_sym_def ne {}} {
$w configure -fg PaleGreen
$w configure -fg green
$w configure -bg [option get . background {}]
} elseif {$inst_spice_sym_def ne {}} {
$w configure -fg red
$w configure -bg [option get . background {}]
} elseif { [file exists [abs_sym_path [$w get]]] } {
$w configure -fg [option get . foreground {}]
$w configure -bg PaleGreen
$w configure -bg green
} else {
$w configure -fg [option get . foreground {}]
$w configure -bg red