revert modified xschem_library/logic/ff.sym for testing

2026-08-18 10:02:56 +02:00 · 2026-08-18 10:02:56 +02:00 · cd839861c3
parent 5ec3c5f2ff
commit cd839861c3
1 changed files with 1 additions and 1 deletions
--- a/xschem_library/logic/ff.sym
+++ b/xschem_library/logic/ff.sym
@ -23,7 +23,7 @@ G {}
 K {type=subcircuit
 vhdl_stop=true 
 verilog_stop=true
-format="@name #~#@@D @pinlist @symname" 
+format="@name @pinlist @symname" 
 template="name=x1 delay=\\"400 ps\\" del=400"
 generic_type="delay=time"}
 V {}