tab context menu: Do not use saved file to decide if symbol or schematic. Use netlist_type

src/xschem.tcl

@@ -5637,19 +5637,20 @@ proc tab_context_menu {tab_but} {
   if {!$found} { set filename {}}
 
 
-  set filetype [is_xschem_file $filename]
 
-  if {$filetype eq {SCHEMATIC}} {
+  set old [xschem get current_win_path]
+  xschem new_schematic switch $win_path {} 0 ;# no draw
+  set filetype [xschem get netlist_type] ;# symbol or spice or vhdl or tedax or verilog
+  xschem new_schematic switch $old {} 0 ;# no draw
+
+  if {$filetype ne {symbol}} {
     set counterpart [abs_sym_path $filename .sym]
     set msg {Open symbol}
     set img CtxmenuSymbol
-  } elseif {$filetype eq {SYMBOL}} {
+  } else {
     set counterpart [abs_sym_path $filename .sch]
     set msg {Open schematic}
     set img CtxmenuSchematic
-  } else {
-    set counterpart {}
-    set msg {}
   }
   # puts $counterpart
 
@@ -5688,7 +5689,7 @@ proc tab_context_menu {tab_but} {
          destroy .ctxmenu
        "
   }
-  if {$filetype eq {SCHEMATIC}} {
+  if {$filetype ne {symbol}} {
     button .ctxmenu.b5 -text {Edit netlist} -padx 3 -pady 0 -anchor w -activebackground grey50 \
        -highlightthickness 0 -image CtxmenuEdit -compound left \
       -font [subst $font] -command "set retval 5; tab_ctx_cmd $tab_but netlist; destroy .ctxmenu"
@@ -5708,7 +5709,7 @@ proc tab_context_menu {tab_but} {
   if {$counterpart ne {}} {
     pack .ctxmenu.b6 -fill x -expand true
   }
-  if {$filetype eq {SCHEMATIC}} {
+  if {$filetype ne {symbol}} {
     pack .ctxmenu.b5 -fill x -expand true
   }
   pack .ctxmenu.b7 -fill x -expand true

xschem_library/inst_sch_select/comp_65nm_read.sym

@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -27,12 +27,12 @@ spice_sym_def="tcleval([read_data_nonewline [abs_sym_path comp_65nm_read.cir]])"
 V {}
 S {}
 E {}
-L 4 -40 -50 -40 50 {}
-L 4 40 0 60 0 {}
-L 4 -60 30 -40 30 {}
-L 4 -40 -50 40 0 {}
-L 4 -40 50 40 0 {}
-L 4 -60 -30 -40 -30 {}
+L 6 -40 -50 -40 50 {}
+L 6 -40 -50 40 0 {}
+L 6 -40 50 40 0 {}
+L 6 40 0 60 0 {}
+L 6 -60 30 -40 30 {}
+L 6 -60 -30 -40 -30 {}
 B 5 -62.5 -32.5 -57.5 -27.5 {name=PLUS dir=in }
 B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out }
 B 5 -62.5 27.5 -57.5 32.5 {name=MINUS dir=in }

xschem_library/inst_sch_select/inst_sch_select.sch

@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -42,7 +42,7 @@ out3
 out4
 out5
 out6"
-color="7 8 9 10 11 12"
+color="9 10 11 12 13 14"
 dataset=-1
 unitx=1
 logx=0
@@ -69,28 +69,28 @@ logx=0
 logy=0
 hilight_wave=-1}
 T {Default instance:
-Uses comp_65nm.sch} 10 -930 0 0 0.4 0.4 { layer=7}
+Uses comp_65nm.sch} 10 -930 0 0 0.4 0.4 { layer=9}
 T {Alternate instance:
-Uses comp_65nm_parax.sch} 10 -720 0 0 0.4 0.4 { layer=8}
+Uses comp_65nm_parax.sch} 10 -720 0 0 0.4 0.4 { layer=10}
 T {Alternate instance:
 Uses comp_65nm_pex
 contained in attribute
 spice_sym_def
-No schematic used} 10 -520 0 0 0.4 0.4 {}
+No schematic used} 10 -520 0 0 0.4 0.4 { layer=11}
 T {Alternate instance:
 Uses comp_65nm_empty.sch
 netlist embedded in global
-spice schematic attribute} 340 -920 0 0 0.4 0.4 { layer=10}
+spice schematic attribute} 340 -920 0 0 0.4 0.4 { layer=12}
 T {Alternate instance:
 Uses spice_sym_def to read in 
 file comp_65nm_file.cir
-no schematic used} 340 -620 0 0 0.4 0.4 { layer=11}
+no schematic used} 340 -620 0 0 0.4 0.4 { layer=13}
 T {The same symbol is simulated with 5 different implementations
 using instance 'schematic' and 'spice_sym_def' attributes} 190 -1040 0 0 0.6 0.6 { layer=4 slant=oblique}
 T {Instance based implementation selection.} 250 -1100 0 0 0.8 0.8 {}
 T {comp_65nm_read.sym:
 symbol has "spice_sym_def"
-attribute and reads in a file} 340 -360 0 0 0.4 0.4 { layer=12}
+attribute and reads in a file} 340 -360 0 0 0.4 0.4 { layer=14}
 C {comp_65nm.sym} 180 -820 0 0 {name=x1}
 C {lab_pin.sym} 120 -850 0 0 {name=p1 lab=PLUS}
 C {lab_pin.sym} 240 -820 0 1 {name=p2 lab=OUT1}