allow "1" / "0" in addition to "true" / "false" in all boolean attributes

This commit is contained in:
stefan schippers 2023-07-14 00:49:51 +02:00
parent 231f3a38d4
commit bf46fd3e7b
17 changed files with 121 additions and 108 deletions

View File

@ -706,40 +706,40 @@ int set_sym_flags(xSymbol *sym)
my_strdup2(_ALLOC_ID_, &sym->type,
get_tok_value(sym->prop_ptr, "type",0));
if(!strcmp(get_tok_value(sym->prop_ptr,"highlight",0), "true"))
if(!strboolcmp(get_tok_value(sym->prop_ptr,"highlight",0), "true"))
sym->flags |= HILIGHT_CONN;
if(!strcmp(get_tok_value(sym->prop_ptr,"hide",0), "true"))
if(!strboolcmp(get_tok_value(sym->prop_ptr,"hide",0), "true"))
sym->flags |= HIDE_INST;
ptr = get_tok_value(sym->prop_ptr,"spice_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= SPICE_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= SPICE_IGNORE;
ptr = get_tok_value(sym->prop_ptr,"verilog_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= VERILOG_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= VERILOG_IGNORE;
ptr = get_tok_value(sym->prop_ptr,"vhdl_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= VHDL_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= VHDL_IGNORE;
ptr = get_tok_value(sym->prop_ptr,"tedax_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= TEDAX_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= TEDAX_IGNORE;
ptr = get_tok_value(sym->prop_ptr,"lvs_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= LVS_IGNORE_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= LVS_IGNORE_OPEN;
dbg(1, "set_sym_flags: inst %s flags=%d\n", sym->name, sym->flags);
return 0;
@ -759,46 +759,46 @@ int set_inst_flags(xInstance *inst)
my_strdup2(_ALLOC_ID_, &(inst->lab), get_tok_value(inst->prop_ptr,"lab",0));
}
}
if(!strcmp(get_tok_value(inst->prop_ptr,"hide",0), "true"))
if(!strboolcmp(get_tok_value(inst->prop_ptr,"hide",0), "true"))
inst->flags |= HIDE_INST;
ptr = get_tok_value(inst->prop_ptr,"spice_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= SPICE_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= SPICE_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"verilog_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= VERILOG_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= VERILOG_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"vhdl_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= VHDL_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= VHDL_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"tedax_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= TEDAX_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= TEDAX_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"lvs_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= LVS_IGNORE_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= LVS_IGNORE_OPEN;
if(!strcmp(get_tok_value(inst->prop_ptr,"hide_texts",0), "true"))
if(!strboolcmp(get_tok_value(inst->prop_ptr,"hide_texts",0), "true"))
inst->flags |= HIDE_SYMBOL_TEXTS;
if(!strcmp(get_tok_value(inst->prop_ptr,"highlight",0), "true"))
if(!strboolcmp(get_tok_value(inst->prop_ptr,"highlight",0), "true"))
inst->flags |= HILIGHT_CONN;
inst->embed = !strcmp(get_tok_value(inst->prop_ptr, "embed", 2), "true");
inst->embed = !strboolcmp(get_tok_value(inst->prop_ptr, "embed", 2), "true");
dbg(1, "set_inst_flags: inst %s flags=%d\n", inst->instname, inst->flags);
return 0;
@ -814,9 +814,9 @@ int set_text_flags(xText *t)
if(t->prop_ptr) {
my_strdup(_ALLOC_ID_, &t->font, get_tok_value(t->prop_ptr, "font", 0));
str = get_tok_value(t->prop_ptr, "hcenter", 0);
t->hcenter = strcmp(str, "true") ? 0 : 1;
t->hcenter = strboolcmp(str, "true") ? 0 : 1;
str = get_tok_value(t->prop_ptr, "vcenter", 0);
t->vcenter = strcmp(str, "true") ? 0 : 1;
t->vcenter = strboolcmp(str, "true") ? 0 : 1;
str = get_tok_value(t->prop_ptr, "layer", 0);
if(str[0]) t->layer = atoi(str);
str = get_tok_value(t->prop_ptr, "slant", 0);
@ -825,7 +825,7 @@ int set_text_flags(xText *t)
str = get_tok_value(t->prop_ptr, "weight", 0);
t->flags |= strcmp(str, "bold") ? 0 : TEXT_BOLD;
str = get_tok_value(t->prop_ptr, "hide", 0);
t->flags |= strcmp(str, "true") ? 0 : HIDE_TEXT;
t->flags |= strboolcmp(str, "true") ? 0 : HIDE_TEXT;
str = get_tok_value(t->prop_ptr, "name", 0);
if(!xctx->tok_size) str = get_tok_value(t->prop_ptr, "floater", 0);
t->flags |= xctx->tok_size ? TEXT_FLOATER : 0;

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@ -190,7 +190,7 @@ void trim_wires(void)
xctx->wire[xctx->wires].sel=0;
xctx->wire[xctx->wires].prop_ptr=NULL;
my_strdup(_ALLOC_ID_, &xctx->wire[xctx->wires].prop_ptr, xctx->wire[j].prop_ptr);
if(!strcmp(get_tok_value(xctx->wire[xctx->wires].prop_ptr,"bus",0), "true"))
if(!strboolcmp(get_tok_value(xctx->wire[xctx->wires].prop_ptr,"bus",0), "true"))
xctx->wire[xctx->wires].bus=1;
else
xctx->wire[xctx->wires].bus=0;
@ -424,7 +424,7 @@ void break_wires_at_point(double x0, double y0)
xctx->wire[xctx->wires].sel=0;
xctx->wire[xctx->wires].prop_ptr=NULL;
my_strdup(_ALLOC_ID_, &xctx->wire[xctx->wires].prop_ptr, xctx->wire[i].prop_ptr);
if(!strcmp(get_tok_value(xctx->wire[xctx->wires].prop_ptr,"bus",0), "true"))
if(!strboolcmp(get_tok_value(xctx->wire[xctx->wires].prop_ptr,"bus",0), "true"))
xctx->wire[xctx->wires].bus=1;
else
xctx->wire[xctx->wires].bus=0;
@ -501,7 +501,7 @@ void break_wires_at_pins(int remove)
xctx->wire[xctx->wires].sel=xctx->wire[i].sel;
xctx->wire[xctx->wires].prop_ptr=NULL;
my_strdup(_ALLOC_ID_, &xctx->wire[xctx->wires].prop_ptr, xctx->wire[i].prop_ptr);
if(!strcmp(get_tok_value(xctx->wire[xctx->wires].prop_ptr,"bus",0), "true"))
if(!strboolcmp(get_tok_value(xctx->wire[xctx->wires].prop_ptr,"bus",0), "true"))
xctx->wire[xctx->wires].bus=1;
else
xctx->wire[xctx->wires].bus=0;
@ -585,7 +585,7 @@ void break_wires_at_pins(int remove)
xctx->wire[xctx->wires].sel=SELECTED;
xctx->wire[xctx->wires].prop_ptr=NULL;
my_strdup(_ALLOC_ID_, &xctx->wire[xctx->wires].prop_ptr, xctx->wire[i].prop_ptr);
if(!strcmp(get_tok_value(xctx->wire[xctx->wires].prop_ptr,"bus",0), "true"))
if(!strboolcmp(get_tok_value(xctx->wire[xctx->wires].prop_ptr,"bus",0), "true"))
xctx->wire[xctx->wires].bus=1;
else
xctx->wire[xctx->wires].bus=0;

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@ -79,6 +79,18 @@ int my_strncasecmp(const char *s1, const char *s2, size_t n)
return tolower(*s1) - tolower(*s2);
}
/* same as strcmp(), but allow "1" for "true" and "0" for "false" */
int strboolcmp(const char *str, const char *boolean)
{
if(!strcmp(boolean, "true")) {
return (strcmp(str, "true") != 0 && strcmp(str,"1") != 0);
} else if(!strcmp(boolean, "false")) {
return (strcmp(str, "false") != 0 && strcmp(str,"0") != 0);
} else {
return strcmp(str, boolean);
}
}
/* return lenght of line and skip */
size_t my_fgets_skip(FILE *fd)
{
@ -831,7 +843,7 @@ static int edit_rect_property(int x)
xctx->rect[c][n].dash = 0;
fill = get_tok_value(xctx->rect[c][n].prop_ptr,"fill", 0);
if(!strcmp(fill, "false")) xctx->rect[c][n].fill = 0;
if(!strboolcmp(fill, "false")) xctx->rect[c][n].fill = 0;
else xctx->rect[c][n].fill = 1;
if( (oldprop && xctx->rect[c][n].prop_ptr && strcmp(oldprop, xctx->rect[c][n].prop_ptr)) ||
@ -889,7 +901,7 @@ static int edit_line_property(void)
my_strdup(_ALLOC_ID_, &xctx->line[c][n].prop_ptr,
(char *) tclgetvar("retval"));
}
xctx->line[c][n].bus = !strcmp(get_tok_value(xctx->line[c][n].prop_ptr,"bus",0), "true");
xctx->line[c][n].bus = !strboolcmp(get_tok_value(xctx->line[c][n].prop_ptr,"bus",0), "true");
dash = get_tok_value(xctx->line[c][n].prop_ptr,"dash",0);
if( strcmp(dash, "") ) {
int d = atoi(dash);
@ -949,7 +961,7 @@ static int edit_wire_property(void)
my_strdup(_ALLOC_ID_, &xctx->wire[k].prop_ptr,(char *) tclgetvar("retval"));
}
bus_ptr = get_tok_value(xctx->wire[k].prop_ptr,"bus",0);
if(!strcmp(bus_ptr, "true")) {
if(!strboolcmp(bus_ptr, "true")) {
double ov, y1, y2;
ov = INT_BUS_WIDTH(xctx->lw) > cadhalfdotsize ? INT_BUS_WIDTH(xctx->lw) : CADHALFDOTSIZE;
if(xctx->wire[k].y1 < xctx->wire[k].y2) { y1 = xctx->wire[k].y1-ov; y2 = xctx->wire[k].y2+ov; }
@ -1011,7 +1023,7 @@ static int edit_arc_property(void)
my_strdup(_ALLOC_ID_, &xctx->arc[c][i].prop_ptr, (char *) tclgetvar("retval"));
}
old_fill = xctx->arc[c][i].fill;
if( !strcmp(get_tok_value(xctx->arc[c][i].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(xctx->arc[c][i].prop_ptr,"fill",0),"true") )
xctx->arc[c][i].fill =1;
else
xctx->arc[c][i].fill =0;
@ -1081,7 +1093,7 @@ static int edit_polygon_property(void)
}
old_fill = xctx->poly[c][i].fill;
old_dash = xctx->poly[c][i].dash;
if( !strcmp(get_tok_value(xctx->poly[c][i].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(xctx->poly[c][i].prop_ptr,"fill",0),"true") )
xctx->poly[c][i].fill =1;
else
xctx->poly[c][i].fill =0;

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@ -268,7 +268,7 @@ static void find_closest_element(double mx,double my)
dbg(2, "find_closest_element(): finding closest element, instances=%d, dist=%.16g\n",i,tmp);
}
} /* end for i */
if( r!=-1 && strcmp(get_tok_value(xctx->inst[r].prop_ptr, "lock", 0), "true") ) {
if( r!=-1 && strboolcmp(get_tok_value(xctx->inst[r].prop_ptr, "lock", 0), "true") ) {
sel.n = r; sel.type = ELEMENT;
}
}

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@ -406,19 +406,19 @@ void netlist_options(int i)
str = get_tok_value(xctx->inst[i].prop_ptr, "lvs_ignore", 0);
if(str[0]) {
/* fprintf(errfp, "netlist_options(): prop_ptr=%s\n", xctx->inst[i].prop_ptr); */
if(!strcmp(str, "true")) tclsetintvar("lvs_ignore", 1);
if(!strboolcmp(str, "true")) tclsetintvar("lvs_ignore", 1);
else tclsetintvar("lvs_.netlist", 0);
}
str = get_tok_value(xctx->inst[i].prop_ptr, "lvs_netlist", 0);
if(str[0]) {
/* fprintf(errfp, "netlist_options(): prop_ptr=%s\n", xctx->inst[i].prop_ptr); */
if(!strcmp(str, "true")) tclsetintvar("lvs_netlist", 1);
if(!strboolcmp(str, "true")) tclsetintvar("lvs_netlist", 1);
else tclsetintvar("lvs_netlist", 0);
}
str = get_tok_value(xctx->inst[i].prop_ptr, "spiceprefix", 0);
if(str[0]) {
/* fprintf(errfp, "netlist_options(): prop_ptr=%s\n", xctx->inst[i].prop_ptr); */
if(!strcmp(str, "false")) tclsetvar("spiceprefix", "0");
if(!strboolcmp(str, "false")) tclsetvar("spiceprefix", "0");
else tclsetvar("spiceprefix", "1");
}
@ -1125,7 +1125,7 @@ static int name_nodes_of_pins_labels_and_propagate()
inst[i].node[0]);
}
/* handle global nodes (global=1 set as symbol property) 28032003 */
if(!strcmp(type,"label") && global_node && !strcmp(global_node, "true")) {
if(!strcmp(type,"label") && global_node && !strboolcmp(global_node, "true")) {
dbg(1, "name_nodes_of_pins_labels_and_propagate(): global node: %s\n",inst[i].node[0]);
record_global_node(1,NULL, inst[i].node[0]);
}

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@ -102,7 +102,7 @@ static void merge_box(FILE *fd)
} else {
ptr[i].dash = 0;
}
if( !strcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"false") )
if( !strboolcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"false") )
ptr[i].fill =0;
else
ptr[i].fill =1;
@ -136,7 +136,7 @@ static void merge_arc(FILE *fd)
ptr[i].prop_ptr=NULL;
ptr[i].sel=0;
load_ascii_string(&ptr[i].prop_ptr, fd);
if( !strcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"true") )
ptr[i].fill =1;
else
ptr[i].fill =0;
@ -192,7 +192,7 @@ static void merge_polygon(FILE *fd)
}
}
load_ascii_string( &ptr[i].prop_ptr, fd);
if( !strcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"true") )
ptr[i].fill =1;
else
ptr[i].fill =0;

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@ -133,9 +133,9 @@ void ps_drawPNG(xRect* r, double x1, double y1, double x2, double y2, int rot, i
my_free(_ALLOC_ID_, &closure.buffer);
png_data = cairo_image_surface_get_data(surface);
invertImage = !strcmp(get_tok_value(r->prop_ptr, "InvertOnExport", 0), "true");
invertImage = !strboolcmp(get_tok_value(r->prop_ptr, "InvertOnExport", 0), "true");
if(!invertImage)
invertImage = !strcmp(get_tok_value(r->prop_ptr, "ps_invert", 0), "true");
invertImage = !strboolcmp(get_tok_value(r->prop_ptr, "ps_invert", 0), "true");
BG_r = 0xFF; BG_g = 0xFF; BG_b = 0xFF;
for (i = 0; i < (png_size_x * png_size_y * 4); i += 4)
{

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@ -1853,7 +1853,7 @@ static void load_wire(FILE *fd)
ptr[i].end1 = ptr[i].end2 = ptr[i].bus = ptr[i].sel = 0;
load_ascii_string( &ptr[i].prop_ptr, fd);
ORDER(ptr[i].x1, ptr[i].y1, ptr[i].x2, ptr[i].y2);
if(!strcmp(get_tok_value(ptr[i].prop_ptr, "bus", 0), "true") ) ptr[i].bus = 1;
if(!strboolcmp(get_tok_value(ptr[i].prop_ptr, "bus", 0), "true") ) ptr[i].bus = 1;
ptr[i].node = NULL;
xctx->wires++;
}
@ -1946,7 +1946,7 @@ static void load_polygon(FILE *fd)
}
}
load_ascii_string( &ptr[i].prop_ptr, fd);
if( !strcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"true") )
ptr[i].fill =1;
else
ptr[i].fill =0;
@ -1986,7 +1986,7 @@ static void load_arc(FILE *fd)
ptr[i].prop_ptr=NULL;
ptr[i].sel=0;
load_ascii_string(&ptr[i].prop_ptr, fd);
if( !strcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"true") )
ptr[i].fill =1;
else
ptr[i].fill =0;
@ -2027,7 +2027,7 @@ static void load_box(FILE *fd)
ptr[i].prop_ptr=NULL;
ptr[i].sel=0;
load_ascii_string( &ptr[i].prop_ptr, fd);
if( !strcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"false") )
if( !strboolcmp(get_tok_value(ptr[i].prop_ptr,"fill",0),"false") )
ptr[i].fill =0;
else
ptr[i].fill =1;
@ -2068,7 +2068,7 @@ static void load_line(FILE *fd)
ptr[i].sel=0;
load_ascii_string( &ptr[i].prop_ptr, fd);
if(!strcmp(get_tok_value(ptr[i].prop_ptr, "bus", 0), "true") )
if(!strboolcmp(get_tok_value(ptr[i].prop_ptr, "bus", 0), "true") )
ptr[i].bus = 1;
else
ptr[i].bus = 0;
@ -3339,7 +3339,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
tmpline.prop_ptr = NULL;
load_ascii_string(&tmpline.prop_ptr, lcc[level].fd);
if( !strcmp(get_tok_value(tmpline.prop_ptr, "symbol_ignore", 0), "true")) {
if( !strboolcmp(get_tok_value(tmpline.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmpline.prop_ptr);
continue;
}
@ -3362,7 +3362,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
}
ORDER(ll[c][i].x1, ll[c][i].y1, ll[c][i].x2, ll[c][i].y2);
dbg(2, "l_s_d(): loaded line: ptr=%lx\n", (unsigned long)ll[c]);
if(!strcmp(get_tok_value(ll[c][i].prop_ptr,"bus", 0), "true") )
if(!strboolcmp(get_tok_value(ll[c][i].prop_ptr,"bus", 0), "true") )
ll[c][i].bus = 1;
else
ll[c][i].bus = 0;
@ -3405,7 +3405,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
tmppoly.prop_ptr=NULL;
load_ascii_string( &tmppoly.prop_ptr, lcc[level].fd);
if( !strcmp(get_tok_value(tmppoly.prop_ptr, "symbol_ignore", 0), "true")) {
if( !strboolcmp(get_tok_value(tmppoly.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmppoly.prop_ptr);
my_free(_ALLOC_ID_, &tmppoly.x);
my_free(_ALLOC_ID_, &tmppoly.y);
@ -3422,7 +3422,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
pp[c][i].prop_ptr = tmppoly.prop_ptr;
pp[c][i].points = poly_points;
if( !strcmp(get_tok_value(pp[c][i].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(pp[c][i].prop_ptr,"fill",0),"true") )
pp[c][i].fill =1;
else
pp[c][i].fill =0;
@ -3455,7 +3455,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
tmparc.prop_ptr = NULL;
load_ascii_string( &tmparc.prop_ptr, lcc[level].fd);
if( !strcmp(get_tok_value(tmparc.prop_ptr, "symbol_ignore", 0), "true")) {
if( !strboolcmp(get_tok_value(tmparc.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmparc.prop_ptr);
continue;
}
@ -3484,7 +3484,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
aa[c][i].x = lcc[level].x0 + rx1; aa[c][i].y = lcc[level].y0 + ry1;
aa[c][i].a = angle;
}
if( !strcmp(get_tok_value(aa[c][i].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(aa[c][i].prop_ptr,"fill",0),"true") )
aa[c][i].fill =1;
else
aa[c][i].fill =0;
@ -3515,7 +3515,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
tmprect.prop_ptr = NULL;
load_ascii_string(&tmprect.prop_ptr, lcc[level].fd);
if( !strcmp(get_tok_value(tmprect.prop_ptr, "symbol_ignore", 0), "true")) {
if( !strboolcmp(get_tok_value(tmprect.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmprect.prop_ptr);
continue;
}
@ -3544,7 +3544,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
continue;
}
dbg(2, "l_s_d(): loaded rect: ptr=%lx\n", (unsigned long)bb[c]);
if( !strcmp(get_tok_value(bb[c][i].prop_ptr,"fill",0),"false") )
if( !strboolcmp(get_tok_value(bb[c][i].prop_ptr,"fill",0),"false") )
bb[c][i].fill =0;
else
bb[c][i].fill =1;
@ -3576,7 +3576,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
get_tok_value(tmptext.prop_ptr, "floater", 2);
if(xctx->tok_size) is_floater = 1; /* get rid of floater texts in LCC symbols */
}
if( !strcmp(get_tok_value(tmptext.prop_ptr, "symbol_ignore", 0), "true") || is_floater) {
if( !strboolcmp(get_tok_value(tmptext.prop_ptr, "symbol_ignore", 0), "true") || is_floater) {
my_free(_ALLOC_ID_, &tmptext.prop_ptr);
my_free(_ALLOC_ID_, &tmptext.txt_ptr);
continue;
@ -3670,7 +3670,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
}
load_ascii_string(&tmpline.prop_ptr, lcc[level].fd);
if( !strcmp(get_tok_value(tmpline.prop_ptr, "symbol_ignore", 0), "true")) {
if( !strboolcmp(get_tok_value(tmpline.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmpline.prop_ptr);
continue;
}
@ -3693,7 +3693,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
ORDER(ll[WIRELAYER][i].x1, ll[WIRELAYER][i].y1, ll[WIRELAYER][i].x2, ll[WIRELAYER][i].y2);
dbg(2, "l_s_d(): loaded line: ptr=%lx\n", (unsigned long)ll[WIRELAYER]);
ll[WIRELAYER][i].dash = 0;
if(!strcmp(get_tok_value(ll[WIRELAYER][i].prop_ptr, "bus", 0), "true"))
if(!strboolcmp(get_tok_value(ll[WIRELAYER][i].prop_ptr, "bus", 0), "true"))
ll[WIRELAYER][i].bus = 1;
else
ll[WIRELAYER][i].bus = 0;
@ -3753,7 +3753,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
!strcmp(symtype, "verilog_preprocessor") ||
!strcmp(symtype, "timescale")
) break;
if(!strcmp(get_tok_value(prop_ptr, "symbol_ignore", 0), "true")) break;
if(!strboolcmp(get_tok_value(prop_ptr, "symbol_ignore", 0), "true")) break;
/* add PINLAYER boxes (symbol pins) at schematic i/o/iopin coordinates. */
if( level==0 && IS_PIN(symtype) ) {
add_pinlayer_boxes(lastr, bb, symtype, prop_ptr, inst_x0, inst_y0);

View File

@ -3004,7 +3004,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
else xctx->inst[inst].flags &= ~PIN_OR_LABEL;
xctx->inst[inst].embed = !strcmp(get_tok_value(xctx->inst[inst].prop_ptr, "embed", 2), "true");
xctx->inst[inst].embed = !strboolcmp(get_tok_value(xctx->inst[inst].prop_ptr, "embed", 2), "true");
my_free(_ALLOC_ID_, &ptr);
}
my_free(_ALLOC_ID_, &name);
@ -3927,7 +3927,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
first = 0;
}
remove = 0;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr, attr, 0), "true")) remove = 1;
if(!strboolcmp(get_tok_value(xctx->inst[i].prop_ptr, attr, 0), "true")) remove = 1;
if(remove) {
my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, NULL));
} else {

View File

@ -784,7 +784,7 @@ void select_element(int i,unsigned short select_mode, int fast, int override_loc
char str[1024]; /* overflow safe */
char s[256]; /* overflow safe */
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr, "lock", 0), "true") &&
if(!strboolcmp(get_tok_value(xctx->inst[i].prop_ptr, "lock", 0), "true") &&
select_mode == SELECTED && !override_lock) return;
my_strncpy(s,xctx->inst[i].prop_ptr!=NULL?xctx->inst[i].prop_ptr:"<NULL>",S(s));
if( !fast )
@ -869,7 +869,7 @@ void select_box(int c, int i, unsigned short select_mode, int fast, int override
char str[1024]; /* overflow safe */
char s[256]; /* overflow safe */
if(!strcmp(get_tok_value(xctx->rect[c][i].prop_ptr, "lock", 0), "true") &&
if(!strboolcmp(get_tok_value(xctx->rect[c][i].prop_ptr, "lock", 0), "true") &&
select_mode == SELECTED && !override_lock) return;
if(!fast)
{

View File

@ -194,7 +194,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
/* already done in global_spice_netlist */
if(!strcmp(type,"netlist_commands") && xctx->netlist_count==0) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[i].prop_ptr, "only_toplevel", 0), "true")) continue;
!strboolcmp(get_tok_value(xctx->inst[i].prop_ptr, "only_toplevel", 0), "true")) continue;
if(!strcmp(type,"netlist_commands")) {
fprintf(fd,"**** begin user architecture code\n");
print_spice_element(fd, i) ; /* this is the element line */
@ -416,12 +416,12 @@ int global_spice_netlist(int global) /* netlister driver */
if (str_hash_lookup(&subckt_table, subckt_name, "", XLOOKUP)==NULL)
{
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
if( split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_netlist",0),"true")==0 )
if( split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_netlist",0),"true")==0 )
err |= vhdl_block_netlist(fd, i);
else if(split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_netlist",0),"true")==0 )
else if(split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_netlist",0),"true")==0 )
err |= verilog_block_netlist(fd, i);
else
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_primitive",0),"true") )
if( strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_primitive",0),"true") )
err |= spice_block_netlist(fd, i);
}
}
@ -541,7 +541,7 @@ int spice_block_netlist(FILE *fd, int i)
my_strdup(_ALLOC_ID_, &name, tcl_hook2(xctx->sym[i].name));
split_f = tclgetboolvar("split_files");
if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"spice_stop",0),"true") )
if(!strboolcmp( get_tok_value(xctx->sym[i].prop_ptr,"spice_stop",0),"true") )
spice_stop=1;
else
spice_stop=0;

View File

@ -152,7 +152,7 @@ void store_arc(int pos, double x, double y, double r, double a, double b,
xctx->arc[rectc][n].prop_ptr = NULL;
my_strdup(_ALLOC_ID_, &xctx->arc[rectc][n].prop_ptr, prop_ptr);
xctx->arc[rectc][n].sel = sel;
if( !strcmp(get_tok_value(xctx->arc[rectc][n].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(xctx->arc[rectc][n].prop_ptr,"fill",0),"true") )
xctx->arc[rectc][n].fill =1;
else
xctx->arc[rectc][n].fill =0;
@ -199,7 +199,7 @@ void store_poly(int pos, double *x, double *y, int points, unsigned int rectc,
xctx->poly[rectc][n].sel = sel;
if( !strcmp(get_tok_value(xctx->poly[rectc][n].prop_ptr,"fill",0),"true") )
if( !strboolcmp(get_tok_value(xctx->poly[rectc][n].prop_ptr,"fill",0),"true") )
xctx->poly[rectc][n].fill =1;
else
xctx->poly[rectc][n].fill =0;
@ -241,7 +241,7 @@ int storeobject(int pos, double x1,double y1,double x2,double y2,
xctx->line[rectc][n].prop_ptr=NULL;
my_strdup(_ALLOC_ID_, &xctx->line[rectc][n].prop_ptr, prop_ptr);
xctx->line[rectc][n].sel=sel;
if( prop_ptr && !strcmp(get_tok_value(prop_ptr, "bus", 0), "true") )
if( prop_ptr && !strboolcmp(get_tok_value(prop_ptr, "bus", 0), "true") )
xctx->line[rectc][n].bus = 1;
else
xctx->line[rectc][n].bus = 0;
@ -279,7 +279,7 @@ int storeobject(int pos, double x1,double y1,double x2,double y2,
xctx->rect[rectc][n].dash = (char) (d >= 0 ? d : 0);
} else
xctx->rect[rectc][n].dash = 0;
if(!strcmp(get_tok_value(xctx->rect[rectc][n].prop_ptr,"fill",0),"false") )
if(!strboolcmp(get_tok_value(xctx->rect[rectc][n].prop_ptr,"fill",0),"false") )
xctx->rect[rectc][n].fill =0;
else
xctx->rect[rectc][n].fill =1;
@ -313,7 +313,7 @@ int storeobject(int pos, double x1,double y1,double x2,double y2,
xctx->wire[n].end1=0;
xctx->wire[n].end2=0;
my_strdup(_ALLOC_ID_, &xctx->wire[n].prop_ptr, prop_ptr);
if(prop_ptr && !strcmp(get_tok_value(prop_ptr,"bus",0), "true")) xctx->wire[n].bus=1;
if(prop_ptr && !strboolcmp(get_tok_value(prop_ptr,"bus",0), "true")) xctx->wire[n].bus=1;
else xctx->wire[n].bus=0;
xctx->wire[n].sel=sel;
xctx->wires++;

View File

@ -51,7 +51,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
/* already done in global_tedax_netlist */
if(!strcmp(type,"netlist_commands") && xctx->netlist_count==0) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[i].prop_ptr, "only_toplevel", 0), "true")) continue;
!strboolcmp(get_tok_value(xctx->inst[i].prop_ptr, "only_toplevel", 0), "true")) continue;
if(!strcmp(type,"netlist_commands")) {
fprintf(fd,"#**** begin user architecture code\n");
print_tedax_element(fd, i) ; /* this is the element line */
@ -76,7 +76,7 @@ static int tedax_block_netlist(FILE *fd, int i)
char filename[PATH_MAX];
char *extra=NULL;
if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"tedax_stop",0),"true") )
if(!strboolcmp( get_tok_value(xctx->sym[i].prop_ptr,"tedax_stop",0),"true") )
tedax_stop=1;
else
tedax_stop=0;

View File

@ -983,7 +983,7 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
for(i=0;i<no_of_pins; ++i)
{
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr;
if(strcmp(get_tok_value(prop,"vhdl_ignore",0), "true")) {
if(strboolcmp(get_tok_value(prop,"vhdl_ignore",0), "true")) {
const char *name = get_tok_value(prop,"name",0);
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
if(!first) fprintf(fd, " , ");
@ -999,7 +999,7 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
for(i=0;i<no_of_pins; ++i) {
xSymbol *ptr = xctx->inst[inst].ptr + xctx->sym;
if(!strcmp( get_tok_value(ptr->rect[PINLAYER][i].prop_ptr,"name",0), token+2)) {
if(strcmp(get_tok_value(ptr->rect[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
if(strboolcmp(get_tok_value(ptr->rect[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
str_ptr = net_name(inst,i, &multip, 0, 1);
fprintf(fd, "----pin(%s) ", str_ptr);
}
@ -1060,7 +1060,7 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
const char *si;
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][n].prop_ptr;
si = get_tok_value(prop, "verilog_ignore",0);
if(strcmp(si, "true")) {
if(strboolcmp(si, "true")) {
str_ptr = net_name(inst,n, &multip, 0, 1);
fprintf(fd, "----pin(%s) ", str_ptr);
}
@ -1478,7 +1478,7 @@ void print_vhdl_element(FILE *fd, int inst)
int_hash_init(&table, 37);
for(i=0;i<no_of_pins; ++i)
{
if(strcmp(get_tok_value(pinptr[i].prop_ptr,"vhdl_ignore",0), "true")) {
if(strboolcmp(get_tok_value(pinptr[i].prop_ptr,"vhdl_ignore",0), "true")) {
const char *name = get_tok_value(pinptr[i].prop_ptr, "name", 0);
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
if( (str_ptr = net_name(inst,i, &multip, 0, 1)) )
@ -1715,7 +1715,7 @@ void print_tedax_subckt(FILE *fd, int symbol)
for(i=0;i<no_of_pins; ++i)
{
if(strcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"tedax_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"tedax_ignore",0), "true")) {
str_ptr=
expandlabel(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"name",0), &multip);
fprintf(fd, "%s ", str_ptr);
@ -1808,7 +1808,7 @@ void print_spice_subckt_nodes(FILE *fd, int symbol)
int_hash_init(&table, 37);
for(i=0;i<no_of_pins; ++i)
{
if(strcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"spice_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"spice_ignore",0), "true")) {
const char *name = get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"name",0);
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
str_ptr= expandlabel(name, &multip);
@ -1824,7 +1824,7 @@ void print_spice_subckt_nodes(FILE *fd, int symbol)
prop = xctx->sym[symbol].rect[PINLAYER][i].prop_ptr;
if(!strcmp(get_tok_value(prop, "name",0), token + 2)) break;
}
if(i<no_of_pins && strcmp(get_tok_value(prop,"spice_ignore",0), "true")) {
if(i<no_of_pins && strboolcmp(get_tok_value(prop,"spice_ignore",0), "true")) {
fprintf(fd, "%s ", expandlabel(token+2, &multip));
}
}
@ -1835,7 +1835,7 @@ void print_spice_subckt_nodes(FILE *fd, int symbol)
get_pin_and_attr(token, &pin_num_or_name, &pin_attr);
pin_number = get_sym_pin_number(symbol, pin_num_or_name);
if(pin_number >= 0 && pin_number < no_of_pins) {
if(strcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][pin_number].prop_ptr,"spice_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][pin_number].prop_ptr,"spice_ignore",0), "true")) {
str_ptr = get_tok_value(xctx->sym[symbol].rect[PINLAYER][pin_number].prop_ptr,"name",0);
fprintf(fd, "%s ", expandlabel(str_ptr, &multip));
}
@ -2073,7 +2073,7 @@ int print_spice_element(FILE *fd, int inst)
for(i=0;i<no_of_pins; ++i)
{
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr;
int spice_ignore = !strcmp(get_tok_value(prop, "spice_ignore", 0), "true");
int spice_ignore = !strboolcmp(get_tok_value(prop, "spice_ignore", 0), "true");
const char *name = get_tok_value(prop, "name", 0);
if(!spice_ignore) {
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
@ -2092,7 +2092,7 @@ int print_spice_element(FILE *fd, int inst)
for(i=0;i<no_of_pins; ++i) {
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr;
if (!strcmp( get_tok_value(prop,"name",0), token+2)) {
if(strcmp(get_tok_value(prop,"spice_ignore",0), "true")) {
if(strboolcmp(get_tok_value(prop,"spice_ignore",0), "true")) {
str_ptr = net_name(inst,i, &multip, 0, 1);
tmp = strlen(str_ptr) +100 ; /* always make room for some extra chars
@ -2159,7 +2159,7 @@ int print_spice_element(FILE *fd, int inst)
const char *si;
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][n].prop_ptr;
si = get_tok_value(prop, "spice_ignore",0);
if(strcmp(si, "true")) {
if(strboolcmp(si, "true")) {
str_ptr = net_name(inst,n, &multip, 0, 1);
tmp = strlen(str_ptr) +100 ; /* always make room for some extra chars
@ -2548,7 +2548,7 @@ void print_tedax_element(FILE *fd, int inst)
const char *si;
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][n].prop_ptr;
si = get_tok_value(prop, "tedax_ignore",0);
if(strcmp(si, "true")) {
if(strboolcmp(si, "true")) {
str_ptr = net_name(inst,n, &multip, 0, 1);
fprintf(fd, "%s", str_ptr);
}
@ -2733,7 +2733,7 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
int first = 1;
int_hash_init(&table, 37);
for(i=0;i<no_of_pins; ++i) {
if(strcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
const char *name = get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"name",0);
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
if(!first) fprintf(fd, " , ");
@ -2808,7 +2808,7 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
const char *si;
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][n].prop_ptr;
si = get_tok_value(prop, "verilog_ignore",0);
if(strcmp(si, "true")) {
if(strboolcmp(si, "true")) {
str_ptr = net_name(inst,n, &multip, 0, 1);
fprintf(fd, "----pin(%s) ", str_ptr);
}
@ -2999,7 +2999,7 @@ void print_verilog_element(FILE *fd, int inst)
for(i=0;i<no_of_pins; ++i)
{
xSymbol *ptr = xctx->inst[inst].ptr + xctx->sym;
if(strcmp(get_tok_value(ptr->rect[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
if(strboolcmp(get_tok_value(ptr->rect[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
const char *name = get_tok_value(ptr->rect[PINLAYER][i].prop_ptr, "name", 0);
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
if( (str_ptr = net_name(inst,i, &multip, 0, 1)) )
@ -3216,8 +3216,8 @@ static char *get_pin_attr(const char *token, int inst, int s_pnetname)
if(!pin_attr_value && is_net_name) {
char *instprop = xctx->inst[inst].prop_ptr;
char *symprop = (xctx->inst[inst].ptr + xctx->sym)->prop_ptr;
if(s_pnetname && (!strcmp(get_tok_value(symprop, "net_name", 0), "true") ||
!strcmp(get_tok_value(instprop, "net_name", 0), "true"))) {
if(s_pnetname && (!strboolcmp(get_tok_value(symprop, "net_name", 0), "true") ||
!strboolcmp(get_tok_value(instprop, "net_name", 0), "true"))) {
prepare_netlist_structs(0);
my_strdup2(_ALLOC_ID_, &pin_attr_value,
xctx->inst[inst].node && xctx->inst[inst].node[n] ? xctx->inst[inst].node[n] : "?");
@ -3233,8 +3233,8 @@ static char *get_pin_attr(const char *token, int inst, int s_pnetname)
char *instprop = xctx->inst[inst].prop_ptr;
char *symprop = (xctx->inst[inst].ptr + xctx->sym)->prop_ptr;
dbg(1, "translate(): resolved_net: %s, symbol %s\n", xctx->current_name, xctx->inst[inst].name);
if(s_pnetname && (!strcmp(get_tok_value(symprop, "net_name", 0), "true") ||
!strcmp(get_tok_value(instprop, "net_name", 0), "true"))) {
if(s_pnetname && (!strboolcmp(get_tok_value(symprop, "net_name", 0), "true") ||
!strboolcmp(get_tok_value(instprop, "net_name", 0), "true"))) {
prepare_netlist_structs(0);
if(xctx->inst[inst].node && xctx->inst[inst].node[n]) {
rn = resolved_net(xctx->inst[inst].node[n]);
@ -3383,7 +3383,7 @@ const char *translate(int inst, const char* s)
for(i=0;i<no_of_pins; ++i) {
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr;
if (!strcmp( get_tok_value(prop,"name",0), token+2)) {
if(strcmp(get_tok_value(prop,"spice_ignore",0), "true")) {
if(strboolcmp(get_tok_value(prop,"spice_ignore",0), "true")) {
const char *str_ptr = net_name(inst,i, &multip, 0, 0);
tmp = strlen(str_ptr) +100 ;
STR_ALLOC(&result, tmp + result_pos, &size);

View File

@ -343,11 +343,11 @@ int global_verilog_netlist(int global) /* netlister driver */
if (str_hash_lookup(&subckt_table, subckt_name, "", XLOOKUP)==NULL)
{
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
if( split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_netlist",0),"true")==0 )
if( split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_netlist",0),"true")==0 )
err |= vhdl_block_netlist(fd, i);
else if(split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_netlist",0),"true")==0 )
else if(split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_netlist",0),"true")==0 )
err |= spice_block_netlist(fd, i);
else if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_primitive",0), "true"))
else if( strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_primitive",0), "true"))
err |= verilog_block_netlist(fd, i);
}
}
@ -427,7 +427,7 @@ int verilog_block_netlist(FILE *fd, int i)
my_strdup(_ALLOC_ID_, &name, tcl_hook2(xctx->sym[i].name));
split_f = tclgetboolvar("split_files");
if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"verilog_stop",0),"true") )
if(!strboolcmp( get_tok_value(xctx->sym[i].prop_ptr,"verilog_stop",0),"true") )
verilog_stop=1;
else
verilog_stop=0;
@ -495,7 +495,7 @@ int verilog_block_netlist(FILE *fd, int i)
tmp=0;
for(j=0;j<xctx->sym[i].rects[PINLAYER]; ++j)
{
if(strcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
const char *name = get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr, "name", 0);
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
if(tmp) fprintf(fd, " ,\n");
@ -524,7 +524,7 @@ int verilog_block_netlist(FILE *fd, int i)
int_hash_init(&table, 37);
for(j=0;j<xctx->sym[i].rects[PINLAYER]; ++j)
{
if(strcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(
xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_type",0));
my_strdup(_ALLOC_ID_, &port_value,
@ -562,7 +562,7 @@ int verilog_block_netlist(FILE *fd, int i)
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, 1, lvs_ignore)) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;
!strboolcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {

View File

@ -303,7 +303,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(j=0;j<xctx->symbols; ++j)
{
if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_primitive",0),"true")==0 ) continue;
if( strboolcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_primitive",0),"true")==0 ) continue;
if(xctx->sym[j].flags & (VHDL_IGNORE | VHDL_SHORT)) continue;
if(lvs_ignore && (xctx->sym[j].flags & LVS_IGNORE)) continue;
if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
@ -328,7 +328,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
int_hash_init(&table, 37);
for(i=0;i<xctx->sym[j].rects[PINLAYER]; ++i)
{
if(strcmp(get_tok_value(xctx->sym[j].rect[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[j].rect[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(
xctx->sym[j].rect[PINLAYER][i].prop_ptr,"sig_type",0));
my_strdup(_ALLOC_ID_, &port_value,
@ -432,11 +432,11 @@ int global_vhdl_netlist(int global) /* netlister driver */
if (str_hash_lookup(&subckt_table, subckt_name, "", XLOOKUP)==NULL)
{
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
if( split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_netlist",0),"true")==0 )
if( split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_netlist",0),"true")==0 )
err |= verilog_block_netlist(fd, i);
else if( split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_netlist",0),"true")==0 )
else if( split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_netlist",0),"true")==0 )
err |= spice_block_netlist(fd, i);
else if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_primitive",0),"true"))
else if( strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_primitive",0),"true"))
err |= vhdl_block_netlist(fd, i);
}
}
@ -510,7 +510,7 @@ int vhdl_block_netlist(FILE *fd, int i)
int lvs_ignore = tclgetboolvar("lvs_ignore");
split_f = tclgetboolvar("split_files");
if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"vhdl_stop",0),"true") )
if(!strboolcmp( get_tok_value(xctx->sym[i].prop_ptr,"vhdl_stop",0),"true") )
vhdl_stop=1;
else
vhdl_stop=0;
@ -565,7 +565,7 @@ int vhdl_block_netlist(FILE *fd, int i)
int_hash_init(&table, 37);
for(j=0;j<xctx->sym[i].rects[PINLAYER]; ++j)
{
if(strcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"vhdl_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"vhdl_ignore",0), "true")) {
my_strdup(_ALLOC_ID_, &sig_type,
get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"sig_type",0));
my_strdup(_ALLOC_ID_, &port_value,
@ -613,7 +613,7 @@ int vhdl_block_netlist(FILE *fd, int i)
get_additional_symbols(1);
for(j=0;j<xctx->symbols; ++j)
{
if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_primitive",0),"true")==0 ) continue;
if( strboolcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_primitive",0),"true")==0 ) continue;
if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
strcmp(xctx->sym[j].type,"subcircuit")!=0))
continue;
@ -640,7 +640,7 @@ int vhdl_block_netlist(FILE *fd, int i)
int_hash_init(&table, 37);
for(k=0;k<xctx->sym[j].rects[PINLAYER]; ++k)
{
if(strcmp(get_tok_value(xctx->sym[j].rect[PINLAYER][k].prop_ptr,"vhdl_ignore",0), "true")) {
if(strboolcmp(get_tok_value(xctx->sym[j].rect[PINLAYER][k].prop_ptr,"vhdl_ignore",0), "true")) {
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(
xctx->sym[j].rect[PINLAYER][k].prop_ptr,"sig_type",0));
my_strdup(_ALLOC_ID_, &port_value,
@ -674,7 +674,7 @@ int vhdl_block_netlist(FILE *fd, int i)
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, 1, lvs_ignore)) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;
!strboolcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {

View File

@ -1457,6 +1457,7 @@ extern char *my_strtok_r(char *str, const char *delim, const char *quote, char *
extern char **parse_cmd_string(const char *cmd, int *argc);
extern int my_strncpy(char *d, const char *s, size_t n);
extern int my_strcasecmp(const char *s1, const char *s2);
extern int strboolcmp(const char *str, const char *boolean);
extern char *my_strcasestr(const char *haystack, const char *needle);
extern double mylog10(double x);
extern double mylog(double x);