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Added new feature "Make schematic and symbol from selected components" with command "xschem make_sch_from_sel" and function make_schematic(..) 

added proc make_symbol_lcc and make_symbol_lcc.awk
sch and sym components to specially process dash in prop_ptr.
This commit is contained in:
Stefan Frederik 2021-05-29 00:45:01 +02:00
parent 6929cc896e
commit bda3d9d426
8 changed files with 4793 additions and 4321 deletions
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2
src/Makefile.in
View File

@ -11,7 +11,7 @@ put /local/src {
# list all files that need to be installed in "$(XSHAREDIR)"
put /local/install_shares {
keys.help xschem.help xschem.tcl break.awk convert_to_verilog2001.awk
flatten.awk flatten_tedax.awk flatten_savenodes.awk make_sym.awk symgen.awk order_labels.awk
flatten.awk flatten_tedax.awk flatten_savenodes.awk make_sym.awk make_sym_lcc.awk symgen.awk order_labels.awk
sort_labels.awk spice.awk tedax.awk verilog.awk vhdl.awk hspice_backannotate.tcl add_custom_menu.tcl
change_index.tcl resources.tcl xschemrc ngspice_backannotate.tcl rawtovcd gschemtoxschem.awk
}

9
src/draw.c
View File

@ -359,6 +359,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
#if HAS_CAIRO==1
char *textfont;
#endif
int dashprop=0, dash=0;
if(xctx->inst[n].ptr == -1) return;
if( (layer != PINLAYER && !enable_layer[layer]) ) return;
@ -369,6 +370,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
} else {
hide = 0;
}
dashprop = atoi(get_tok_value(xctx->inst[n].prop_ptr, "dash", 0));
type = (xctx->inst[n].ptr+ xctx->sym)->type;
if(layer==0) {
x1=X_TO_SCREEN(xctx->inst[n].x1+xoffset); /* 20150729 added xoffset, yoffset */
@ -419,13 +421,16 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
for(j=0;j< symptr->lines[layer];j++)
{
line = (symptr->line[layer])[j];
dash = line.dash;
if (line.dash == 0 && dashprop > 0 && layer==4)
dash = dashprop;
ROTATION(rot, flip, 0.0,0.0,line.x1,line.y1,x1,y1);
ROTATION(rot, flip, 0.0,0.0,line.x2,line.y2,x2,y2);
ORDER(x1,y1,x2,y2);
if(line.bus)
drawline(c,THICK, x0+x1, y0+y1, x0+x2, y0+y2, line.dash);
drawline(c,THICK, x0+x1, y0+y1, x0+x2, y0+y2, dash);
else
drawline(c,what, x0+x1, y0+y1, x0+x2, y0+y2, line.dash);
drawline(c,what, x0+x1, y0+y1, x0+x2, y0+y2, dash);
}
for(j=0;j< symptr->polygons[layer];j++)
{

381
src/make_sym_lcc.awk Normal file
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@ -0,0 +1,381 @@
#!/usr/bin/awk -f
#
# File: make_sym_lcc.awk
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2020 Stefan Frederik Schippers
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#
BEGIN{
width=150
}
FNR == 1 {
if (_filename_ != "") endfile(_filename_)
_filename_ = FILENAME
beginfile(FILENAME)
}
END { endfile(_filename_) }
function beginfile(f)
{
sym=name=f
sub(/^.*\//,"",name)
name_ext=name
sub(/\.sch.*$/,"",name)
sub(/\.sch.*$/,".sym",sym)
print "**** symbol-izing: " sym " ****"
template="" ; start=0
while((getline symline <sym) >0) {
if(symline ~ /^[GK] \{/ ) start=1
if(start) template=template symline "\n"
if(symline ~ /\} *$/) start=0
}
close(sym)
size=2.5
space=20
lwidth=20
textdist=5
labsize=0.2
titlesize=0.3
text_voffset=10
lab_voffset=4
ip=op=n_pin=n_p=n_l=0
print "v {xschem version=2.9.8 file_version=1.2}" > sym
if(template=="") {
printf "%s", "K {type=subcircuit\nformat=\"@name @pinlist @symname\"\n" >sym
printf "%s\n", "template=\"name=x1\"" >sym
printf "%s", "}\n" >sym
}
else print template >sym
}
/^C \{.*generic_pin(\.sym)?\}/{
get_end_line()
process_line()
type_pin[n_pin]=generic_type
dir_pin[n_pin]="generic"
x_pin[n_pin] = $3+0 # y coordinate of pin 20140519
y_pin[n_pin] = $4+0 # y coordinate of pin 20140519
rotation_pin[n_pin] = $5+0 # y coordinate of pin 20140519
flip_pin[n_pin] = $6+0 # y coordinate of pin 20140519
index_pin[n_pin] = n_pin # one level indirection for sorting pins 20140519
value_pin[n_pin]=value
label_pin[n_pin] = pin_label
props_pin[n_pin] = rest_of_props()
n_pin++
ip++
}
/^[LP] /{
get_end_line()
process_box_line()
box[n_p]=$0
n_p++
}
/^C \{.*ipin(\.sym)?\}/{
get_end_line()
process_line()
type_pin[n_pin]=sig_type
verilog_pin[n_pin]=verilog_type
dir_pin[n_pin]="ipin"
x_pin[n_pin] = $3+0 # y coordinate of pin 20140519
y_pin[n_pin] = $4+0 # y coordinate of pin 20140519
rotation_pin[n_pin] = $5+0 # y coordinate of pin 20140519
flip_pin[n_pin] = $6+0 # y coordinate of pin 20140519
index_pin[n_pin] = n_pin # one level indirection 20140519
value_pin[n_pin]=value
label_pin[n_pin] = pin_label
props_pin[n_pin] = rest_of_props()
n_pin++
ip++
}
$0 ~ /^C \{.*opin(\.sym)?\}/ && $0 !~ /^C \{.*iopin(\.sym)?\}/ {
get_end_line()
process_line()
type_pin[n_pin]=sig_type
verilog_pin[n_pin]=verilog_type
dir_pin[n_pin]="opin"
x_pin[n_pin] = $3+0 # y coordinate of pin 20140519
y_pin[n_pin] = $4+0 # y coordinate of pin 20140519
rotation_pin[n_pin] = $5+0 # y coordinate of pin 20140519
flip_pin[n_pin] = $6+0 # y coordinate of pin 20140519
index_pin[n_pin] = n_pin # one level indirection 20140519
value_pin[n_pin]=value
label_pin[n_pin] = pin_label
props_pin[n_pin] = rest_of_props()
n_pin++
op++
}
/^C \{.*iopin(\.sym)?\}/{
print "iopin"
get_end_line()
process_line()
type_pin[n_pin]=sig_type
verilog_pin[n_pin]=verilog_type
dir_pin[n_pin]="iopin"
x_pin[n_pin] = $3+0 # y coordinate of pin 20140519
y_pin[n_pin] = $4+0 # y coordinate of pin 20140519
rotation_pin[n_pin] = $5+0 # y coordinate of pin 20140519
flip_pin[n_pin] = $6+0 # y coordinate of pin 20140519
index_pin[n_pin] = n_pin # one level indirection 20140519
value_pin[n_pin]=value
label_pin[n_pin] = pin_label
props_pin[n_pin] = rest_of_props()
n_pin++
op++
}
function rest_of_props()
{
sub(/^C \{[^}]+\}.*\{/,"")
sub(/\}[ \t]*$/, "")
sub(/verilog_type[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
sub(/sig_type[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
sub(/lab[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
sub(/value[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
sub(/^[ \t]*$/, "")
return $0
}
function process_line()
{
print "process_line"
sig_type="" #20070726 # "std_logic"
verilog_type= "" # 20070726 "wire" #09112003
pin_label=""
value=""
generic_type=""
if($0 ~ /^.*lab=/)
{
pin_label=$0
sub(/^.*lab=/,"",pin_label)
sub(/[ }].*$/,"",pin_label)
}
if($0 ~ /^.*verilog_type=/) #09112003
{
verilog_type=$0
sub(/^.*verilog_type=/,"",verilog_type)
sub(/[}].*$/,"",verilog_type)
sub(/ $/,"",verilog_type)
}
if($0 ~ /^.*sig_type=/)
{
sig_type=$0
sub(/^.*sig_type=/,"",sig_type)
sub(/[ }].*$/,"",sig_type)
}
if($0 ~ /^.*generic_type=/)
{
generic_type=$0
sub(/^.*generic_type=/,"",generic_type)
sub(/[}].*$/,"",generic_type)
sub(/[a-zA-Z0-9]+=.*$/,"",generic_type) #03062002, allow spaces
print "------------------------" $0 "-->" generic_type
}
if($0 ~ /^.*value=/)
{
value=$0
if(value ~ /value="/)
{
sub(/^.*value="/,"",value)
value= "\"" substr(value,1, match(value, /[^\\]"/) ) "\""
}
else
{
sub(/^.*value=/,"",value)
sub(/[ }].*$/,"",value)
}
}
#print "process_line: returning:" $0
# print "process_line: pin_label=" pin_label " verilog_type=" verilog_type
}
function process_box_line()
{
print "process_box_line"
if($0 ~ /^.*dash=/)
{
sub(/dash=[0-9]/,"dash=0")
}
print "process_box_line: returning:" $0
# print "process_line: pin_label=" pin_label " verilog_type=" verilog_type
}
## join lines like this:
## C {ipin.sym} ........ {lab=xxx
## verilog_type=reg}
function get_end_line()
{
print "get_end_line"
while($0 !~ /\}[ \t]*$/) {
a=$0
getline
$0 = a " " $0
}
}
function endfile(f) {
n=ip;if(op>n) n=op
if(n==0) n=1
m=(n-1)/2
y=-m*space
x=-width
box_minx=box_maxx=box_miny=box_maxy=0
for(ii=0;ii<n_p;ii++)
{
print box[ii] >sym
awk split(box[ii],a," ");
box_type=a[1]
if (box_type=="P")
{
box_num_vertices = a[3]
for (j=0;j<box_num_vertices*2;j+=2)
{
if (box_minx==0 || box_minx > a[4+j]) box_minx=a[4+j]
if (box_maxx==0 || box_maxx < a[4+j]) box_maxx=a[4+j]
if (box_miny==0 || box_miny > a[4+j+1]) box_miny=a[4+j+1]
if (box_maxy==0 || box_maxy < a[4+j+1]) box_maxy=a[4+j+1]
}
print "(" box_minx "," box_miny ") and (" box_maxx "," box_maxy ")"
}
if (box_type=="L")
{
if (box_minx==0 || box_minx > a[3]) box_minx=a[3]
if (box_maxx==0 || box_maxx < a[3]) box_maxx=a[3]
if (box_minx==0 || box_minx > a[5]) box_minx=a[5]
if (box_maxx==0 || box_maxx < a[5]) box_maxx=a[5]
if (box_miny==0 || box_miny > a[4]) box_miny=a[4]
if (box_maxy==0 || box_maxy < a[4]) box_maxy=a[4]
if (box_miny==0 || box_miny > a[6]) box_miny=a[6]
if (box_maxy==0 || box_maxy < a[6]) box_maxy=a[6]
#print "(" box_minx "," box_miny ") and (" box_maxx "," box_maxy ")"
}
}
#print "Final: (" box_minx "," box_miny ") and (" box_maxx "," box_maxy ")"
#print "T {@symname}" ,(box_maxx+box_minx)/2, (box_maxy+box_miny)/2,0,0,
# titlesize, titlesize, "{}" >sym
print "T {@symname}",box_minx-lwidth+5, box_miny-text_voffset,0,0,labsize, labsize,"{}" >sym
print "T {@name}",box_maxx-lwidth+5, box_miny-text_voffset,0,0,labsize, labsize,"{}" >sym
for(ii=0;ii<n_pin;ii++)
{
i = index_pin[ii] # 20140519
dir=dir_pin[i]
value=value_pin[i]
sig_type=type_pin[i]
verilog_type=verilog_pin[i]
vert = verilog_type ? (" verilog_type=" verilog_type) : ""
vhdt = sig_type ? (" sig_type=" sig_type) : ""
if(dir=="generic")
{
printf "B 3 " (x_pin[i]-size) " " (y_pin[i]-size) " " (x_pin[i]+size) " " (y_pin[i]+size) \
" {name=" label_pin[i] " generic_type=" sig_type " " >sym
if(value !="") printf "value=" value " " >sym
printf props_pin[i] > sym
printf "}\n" >sym
x = get_text_x(label_pin[i], x_pin[i], y_pin[i], box_minx, box_maxx, box_miny, box_maxy)
y = get_text_y(label_pin[i], x_pin[i], y_pin[i], box_minx, box_maxx, box_miny, box_maxy)
print "T {" label_pin[i] "}",x,y,0,0,labsize, labsize, "{}" >sym
}
if(dir=="ipin")
{
printf "B 5 " (x_pin[i]-size) " " (y_pin[i]-size) " " (x_pin[i]+size) " " (y_pin[i]+size) \
" {name=" label_pin[i] vhdt vert " dir=in " >sym
if(value !="") printf "value=" value " " >sym
printf props_pin[i] > sym
printf "}\n" >sym
x = get_text_x(label_pin[i], x_pin[i], y_pin[i], box_minx, box_maxx, box_miny, box_maxy)
y = get_text_y(label_pin[i], x_pin[i], y_pin[i], box_minx, box_maxx, box_miny, box_maxy)
print "T {" label_pin[i] "}",x,y,0,0,labsize, labsize, "{}" >sym
}
if(dir=="opin")
{
printf "B 5 " (x_pin[i]-size) " " (y_pin[i]-size) " " (x_pin[i]+size) " " (y_pin[i]+size) \
" {name=" label_pin[i] vhdt vert " dir=out " >sym
if(value !="") printf "value=" value " " >sym
printf props_pin[i] > sym
printf "}\n" >sym
x = get_text_x(label_pin[i], x_pin[i], y_pin[i], box_minx, box_maxx, box_miny, box_maxy)
y = get_text_y(label_pin[i], x_pin[i], y_pin[i], box_minx, box_maxx, box_miny, box_maxy)
print "T {" label_pin[i] "}",x,y,0,0,labsize, labsize, "{}" >sym
}
if(dir=="iopin")
{
printf "B 5 " (x_pin[i]-size) " " (y_pin[i]-size) " " (x_pin[i]+size) " " (y_pin[i]+size) \
" {name=" label_pin[i] vhdt vert " dir=inout " >sym
if(value !="") printf "value=" value " " >sym
printf props_pin[i] > sym
printf "}\n" >sym
x = get_text_x(label_pin[i], x_pin[i], y_pin[i], box_minx, box_maxx, box_miny, box_maxy)
y = get_text_y(label_pin[i], x_pin[i], y_pin[i], box_minx, box_maxx, box_miny, box_maxy)
print "T {" label_pin[i] "}",x,y,0,0,labsize, labsize, "{}" >sym
}
}
close(sym)
}
function get_text_x(str, x, y, box_minx, box_maxx, box_miny, box_maxy)
{
len = length(str)
if (x == box_minx) # On the left hand side
{
return(x+lwidth+textdist)
}
if (x == box_maxx) # On the right hand side
{
return(x-len-lwidth-textdist)
}
# In between left and right
return(x)
}
function get_text_y(str, x, y, box_minx, box_maxx, box_miny, box_maxy)
{
if (y == box_miny) # On the top line
{
return(y+lwidth+textdist)
}
if (y == box_maxy) # On the bottom line
{
return(y-lwidth-textdist)
}
return(y-lab_voffset)
}

8
src/psprint.c
View File

@ -497,6 +497,7 @@ static void ps_draw_symbol(int n,int layer, short tmp_flip, short rot, double xo
xPoly polygon;
xSymbol *symptr;
char *textfont;
int dashprop=0, dash = 0;
if(xctx->inst[n].ptr == -1) return;
if( (layer != PINLAYER && !enable_layer[layer]) ) return;
@ -521,7 +522,7 @@ static void ps_draw_symbol(int n,int layer, short tmp_flip, short rot, double xo
dbg(1, "draw_symbol(): skippinginst %d\n", n);
return;
}
dashprop = atoi(get_tok_value(xctx->inst[n].prop_ptr, "dash", 0));
flip = xctx->inst[n].flip;
if(tmp_flip) flip = !flip;
rot = (xctx->inst[n].rot + rot ) & 0x3;
@ -532,10 +533,13 @@ static void ps_draw_symbol(int n,int layer, short tmp_flip, short rot, double xo
for(j=0;j< (xctx->inst[n].ptr+ xctx->sym)->lines[layer];j++)
{
line = ((xctx->inst[n].ptr+ xctx->sym)->line[layer])[j];
dash = line.dash;
if (line.dash == 0 && dashprop > 0 && layer==4)
dash = dashprop;
ROTATION(rot, flip, 0.0,0.0,line.x1,line.y1,x1,y1);
ROTATION(rot, flip, 0.0,0.0,line.x2,line.y2,x2,y2);
ORDER(x1,y1,x2,y2);
ps_drawline(layer, x0+x1, y0+y1, x0+x2, y0+y2, line.dash);
ps_drawline(layer, x0+x1, y0+y1, x0+x2, y0+y2, dash);
}
for(j=0;j< (xctx->inst[n].ptr+ xctx->sym)->polygons[layer];j++)
{

69
src/save.c
View File

@ -276,7 +276,7 @@ void save_embedded_symbol(xSymbol *s, FILE *fd)
}
}
void save_inst(FILE *fd)
void save_inst(FILE *fd, int select_only)
{
int i, oldversion;
xInstance *ptr;
@ -287,6 +287,7 @@ void save_inst(FILE *fd)
for(i=0;i<xctx->symbols;i++) xctx->sym[i].flags &=~EMBEDDED;
for(i=0;i<xctx->instances;i++)
{
if (select_only && ptr[i].sel != SELECTED) continue;
fputs("C ", fd);
if(oldversion) {
my_strdup(57, &tmp, add_ext(ptr[i].name, ".sym"));
@ -307,7 +308,7 @@ void save_inst(FILE *fd)
}
}
void save_wire(FILE *fd)
void save_wire(FILE *fd, int select_only)
{
int i;
xWire *ptr;
@ -315,19 +316,21 @@ void save_wire(FILE *fd)
ptr=xctx->wire;
for(i=0;i<xctx->wires;i++)
{
if (select_only && ptr[i].sel != SELECTED) continue;
fprintf(fd, "N %.16g %.16g %.16g %.16g ",ptr[i].x1, ptr[i].y1, ptr[i].x2,
ptr[i].y2);
save_ascii_string(ptr[i].prop_ptr,fd, 1);
}
}
void save_text(FILE *fd)
void save_text(FILE *fd, int select_only)
{
int i;
xText *ptr;
ptr=xctx->text;
for(i=0;i<xctx->texts;i++)
{
if (select_only && ptr[i].sel != SELECTED) continue;
fprintf(fd, "T ");
save_ascii_string(ptr[i].txt_ptr,fd, 0);
fprintf(fd, " %.16g %.16g %hd %hd %.16g %.16g ",
@ -337,7 +340,7 @@ void save_text(FILE *fd)
}
}
void save_polygon(FILE *fd)
void save_polygon(FILE *fd, int select_only)
{
int c, i, j;
xPoly *ptr;
@ -346,6 +349,7 @@ void save_polygon(FILE *fd)
ptr=xctx->poly[c];
for(i=0;i<xctx->polygons[c];i++)
{
if (select_only && ptr[i].sel != SELECTED) continue;
fprintf(fd, "P %d %d ", c,ptr[i].points);
for(j=0;j<ptr[i].points;j++) {
fprintf(fd, "%.16g %.16g ", ptr[i].x[j], ptr[i].y[j]);
@ -355,7 +359,7 @@ void save_polygon(FILE *fd)
}
}
void save_arc(FILE *fd)
void save_arc(FILE *fd, int select_only)
{
int c, i;
xArc *ptr;
@ -364,6 +368,7 @@ void save_arc(FILE *fd)
ptr=xctx->arc[c];
for(i=0;i<xctx->arcs[c];i++)
{
if (select_only && ptr[i].sel != SELECTED) continue;
fprintf(fd, "A %d %.16g %.16g %.16g %.16g %.16g ", c,ptr[i].x, ptr[i].y,ptr[i].r,
ptr[i].a, ptr[i].b);
save_ascii_string(ptr[i].prop_ptr,fd, 1);
@ -371,7 +376,7 @@ void save_arc(FILE *fd)
}
}
void save_box(FILE *fd)
void save_box(FILE *fd, int select_only)
{
int c, i;
xRect *ptr;
@ -380,6 +385,7 @@ void save_box(FILE *fd)
ptr=xctx->rect[c];
for(i=0;i<xctx->rects[c];i++)
{
if (select_only && ptr[i].sel != SELECTED) continue;
fprintf(fd, "B %d %.16g %.16g %.16g %.16g ", c,ptr[i].x1, ptr[i].y1,ptr[i].x2,
ptr[i].y2);
save_ascii_string(ptr[i].prop_ptr,fd, 1);
@ -387,7 +393,7 @@ void save_box(FILE *fd)
}
}
void save_line(FILE *fd)
void save_line(FILE *fd, int select_only)
{
int c, i;
xLine *ptr;
@ -396,6 +402,7 @@ void save_line(FILE *fd)
ptr=xctx->line[c];
for(i=0;i<xctx->lines[c];i++)
{
if (select_only && ptr[i].sel != SELECTED) continue;
fprintf(fd, "L %d %.16g %.16g %.16g %.16g ", c,ptr[i].x1, ptr[i].y1,ptr[i].x2,
ptr[i].y2 );
save_ascii_string(ptr[i].prop_ptr,fd, 1);
@ -447,13 +454,13 @@ void write_xschem_file(FILE *fd)
fprintf(fd, "E ");
save_ascii_string(xctx->schtedaxprop,fd, 1);
save_line(fd);
save_box(fd);
save_arc(fd);
save_polygon(fd);
save_text(fd);
save_wire(fd);
save_inst(fd);
save_line(fd, 0);
save_box(fd, 0);
save_arc(fd, 0);
save_polygon(fd, 0);
save_text(fd, 0);
save_wire(fd, 0);
save_inst(fd, 0);
}
static void load_text(FILE *fd)
@ -917,6 +924,40 @@ void make_symbol(void)
}
void make_schematic(const char *schname)
{
FILE *fd=NULL;
rebuild_selected_array();
if (!xctx->lastsel) return;
if (!(fd = fopen(schname, "w")))
{
fprintf(errfp, "make_schematic(): problems opening file %s \n", schname);
tcleval("alert_ {file opening for write failed!} {}");
return;
}
fprintf(fd, "v {xschem version=%s file_version=%s}\n", XSCHEM_VERSION, XSCHEM_FILE_VERSION);
fprintf(fd, "G {}");
fputc('\n', fd);
fprintf(fd, "V {}");
fputc('\n', fd);
fprintf(fd, "E {}");
fputc('\n', fd);
fprintf(fd, "S {}");
fputc('\n', fd);
fprintf(fd, "K {type=subcircuit\nformat=\"@name @pinlist @symname\"\n");
fprintf(fd, "%s\n", "template=\"name=x1\"");
fprintf(fd, "%s", "}\n");
fputc('\n', fd);
save_line(fd, 1);
save_box(fd, 1);
save_arc(fd, 1);
save_polygon(fd, 1);
save_text(fd, 1);
save_wire(fd, 1);
save_inst(fd, 1);
fclose(fd);
}
/* ALWAYS call with absolute path in schname!!! */
int save_schematic(const char *schname) /* 20171020 added return value */
{

33
src/scheduler.c
View File

@ -1048,6 +1048,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
printf(" place new symbol, asking filename\n");
printf(" xschem make_symbol\n");
printf(" make symbol view from current schematic\n");
printf(" xschem make_sch_from_sel\n");
printf(" make schematic view from selected components\n");
printf(" xschem place_text\n");
printf(" place new text\n");
printf(" xschem debug n\n");
@ -1476,7 +1478,36 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
Tcl_ResetResult(interp);
}
else if (!strcmp(argv[1], "make_sch_from_sel"))
{
char filename[PATH_MAX]="";
cmd_found = 1;
my_snprintf(name, S(name), "save_file_dialog {Save file} .sch.sym INITIALLOADDIR");
tcleval(name);
my_strncpy(filename, tclresult(), S(filename));
if (!strcmp(filename, xctx->sch[xctx->currsch])) {
if (has_x)
tcleval("tk_messageBox -type ok -message {Cannot overwrite current schematic}");
}
else if (strlen(filename)) {
make_schematic(filename);
delete();
place_symbol(-1, filename, 0, 0, 0, 0, NULL, 4, 1);
if (has_x)
{
my_snprintf(name, S(name), "tk_messageBox -type okcancel -message {do you want to make symbol view for %s ?}", filename);
tcleval(name);
}
if (!has_x || !strcmp(tclresult(), "ok")) {
my_snprintf(name, S(name), "make_symbol_lcc {%s}", filename);
dbg(1, "make_symbol_lcc(): making symbol: name=%s\n", filename);
tcleval(name);
}
}
Tcl_ResetResult(interp);
}
else if(!strcmp(argv[1],"merge"))
{
cmd_found = 1;

1
src/xschem.h
View File

@ -873,6 +873,7 @@ extern const char *rel_sym_path(const char *s);
extern const char *abs_sym_path(const char *s, const char *ext);
extern const char *add_ext(const char *f, const char *ext);
extern void make_symbol(void);
extern void make_schematic(const char *schname);
extern const char *get_sym_template(char *s, char *extra);
/* bit0: invoke change_linewidth(), bit1: centered zoom */
extern void zoom_full(int draw, int sel, int flags, double shrink);

8611
src/xschem.tcl
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