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fix a small memory leak in delete_schematic_data()

This commit is contained in:
stefan schippers 2025-05-07 16:11:21 +02:00
parent 8f8b7e2247
commit b122a8abef
2 changed files with 12 additions and 10 deletions
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6
src/xinit.c
View File

@ -717,9 +717,9 @@ static void delete_schematic_data(int delete_pixmap)
clear_all_hilights(); /* data structs for hilighting nets/instances */ clear_all_hilights(); /* data structs for hilighting nets/instances */
get_unnamed_node(0, 0, 0); /* net### enumerator used for netlisting */ get_unnamed_node(0, 0, 0); /* net### enumerator used for netlisting */
clear_drawing(); clear_drawing();
if(has_x && delete_pixmap) { if(delete_pixmap) {
resetwin(0, 1, 1, 0, 0); /* delete preview pixmap, delete cairo surfaces */ resetwin(0, 1, 1, 0, 0); /* delete preview pixmap, delete cairo surfaces */
free_gc(); if(has_x) free_gc();
} }
/* delete instances, wires, lines, rects, arcs, polys, texts, hash_inst, hash_wire, /* delete instances, wires, lines, rects, arcs, polys, texts, hash_inst, hash_wire,
* inst & wire .node fields, instance name hash */ * inst & wire .node fields, instance name hash */
@ -2132,7 +2132,7 @@ void create_memory_cairo_ctx(int what)
static void resetcairo(int create, int clear, int force_or_resize) static void resetcairo(int create, int clear, int force_or_resize)
{ {
#if HAS_CAIRO==1 #if HAS_CAIRO==1
dbg(1, "resetcairo() %d, %d, %d\n", create, clear, force_or_resize); dbg(0, "resetcairo() %d, %d, %d\n", create, clear, force_or_resize);
if(clear && force_or_resize) { if(clear && force_or_resize) {
/* xctx->cairo_save_sfc is based on pixmap and pixmaps are not resizeable, so on resize /* xctx->cairo_save_sfc is based on pixmap and pixmaps are not resizeable, so on resize
* we must destroy & recreate everything. xctx->cairo_sfc can be resized using cairo_*_surface_set_size * we must destroy & recreate everything. xctx->cairo_sfc can be resized using cairo_*_surface_set_size

16
xschem_library/ngspice_verilog_cosim/tb_sar_adc.sch
View File

@ -12,8 +12,8 @@ ypos2=4.2824898
divy=5 divy=5
subdivy=1 subdivy=1
unity=1 unity=1
x1=0 x1=2.7777218e-05
x2=0.00025 x2=9.3313218e-05
divx=5 divx=5
subdivx=1 subdivx=1
xlabmag=1.0 xlabmag=1.0
@ -45,8 +45,8 @@ ypos2=2
divy=5 divy=5
subdivy=1 subdivy=1
unity=1 unity=1
x1=0 x1=2.7777218e-05
x2=0.00025 x2=9.3313218e-05
divx=5 divx=5
subdivx=1 subdivx=1
xlabmag=1.0 xlabmag=1.0
@ -56,11 +56,13 @@ unitx=1
logx=0 logx=0
logy=0 logy=0
digital=0 digital=0
color="4 8 10" color="4 8 10 9"
node="INPUT node="INPUT
xtest.test_v xtest.test_v
i(vamm)" i(vamm)
linewidth_mult=1} xtest.sample 0.05 *"
linewidth_mult=1
hcursor1_y=1.0550322}
T { A simple DAC so that the result may be compared to the input.} 800 -250 0 0 0.4 0.4 {} T { A simple DAC so that the result may be compared to the input.} 800 -250 0 0 0.4 0.4 {}
T {Analog conversion for plotting} 220 -140 0 0 0.4 0.4 {} T {Analog conversion for plotting} 220 -140 0 0 0.4 0.4 {}
T {This is an example of a true mixed mode T {This is an example of a true mixed mode