Visual Ngspice/VACASK analysis setup.

This commit is contained in:
Árpád Bűrmen 2025-09-23 10:19:06 +02:00
parent 34001d7ff0
commit aa72bed12b
21 changed files with 1289 additions and 0 deletions

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@ -209,6 +209,11 @@ int hook_postarg()
append("/local/xschem/xschem-lib-path", "/");
append("/local/xschem/xschem-lib-path", "share/doc/xschem/rom8k");
append("/local/xschem/xschem-lib-path", ":");
append("/local/xschem/xschem-lib-path", get("/local/xschem/prefix"));
append("/local/xschem/xschem-lib-path", "/");
append("/local/xschem/xschem-lib-path", "share/doc/xschem/analyses");
}
return 0;
}

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@ -2559,6 +2559,10 @@ int Tcl_AppInit(Tcl_Interp *inter)
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/rom8k",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/analyses",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
}
tclsetintvar("running_in_src_dir", running_in_src_dir);
#else /* windows */

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@ -27,6 +27,7 @@
#### <install_root>/share/doc/xschem/binto7seg
#### <install_root>/share/doc/xschem/pcb
#### <install_root>/share/doc/xschem/rom8k
#### <install_root>/share/doc/xschem/analyses
#### For testing in build src directory
#### if unset following paths are set and maintained if existing:
@ -42,6 +43,7 @@
#### ../xschem_library/binto7seg
#### ../xschem_library/pcb
#### ../xschem_library/rom8k
#### ../xschem_library/analyses
#### For testing after installation: uncomment following lines
# set xschem_doc_dir [file dirname ${XSCHEM_SHAREDIR}]/doc/xschem
@ -58,6 +60,7 @@
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/binto7seg
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/pcb
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/rom8k
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/analyses
#### Optional, often not needed...
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/symgen
# append XSCHEM_LIBRARY_PATH :${xschem_doc_dir}/xTAG
@ -78,6 +81,7 @@
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/binto7seg"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/pcb"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/rom8k"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/analyses"
#### Optional, often not needed...
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/symgen"
# append XSCHEM_LIBRARY_PATH ";${xschem_doc_dir}/xTAG"

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@ -45,6 +45,10 @@ install: FORCE
$(SCCBOX) install -f -d gschem_import/*.sym "$(XDOCDIR)"/gschem_import
$(SCCBOX) install -f -d gschem_import/*.sch "$(XDOCDIR)"/gschem_import
$(SCCBOX) install -f -d gschem_import/sym/*.sym "$(XDOCDIR)"/gschem_import/sym
$(SCCBOX) install -f -d analyses/*.sch "$(XDOCDIR)"/analyses
$(SCCBOX) install -f -d analyses/*.sym "$(XDOCDIR)"/analyses
$(SCCBOX) install -f -d analyses/*.init.tcl "$(XDOCDIR)"/analyses
$(SCCBOX) install -f -d analyses/README.md "$(XDOCDIR)"/analyses
uninstall: FORCE
$(SCCBOX) rm -f "$(system_library_dir)"/* \

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@ -0,0 +1,41 @@
# Visual simulation setup library
This library makes it possible to set up simulations in a way similar to that in Qucs. Each analysis is represented by a symbol. Symbols (e.g. `op.sym`, `ac.sym`, ...) have attributes that specify the analysis parameters. The instances of these symbols are netlisted as commands in the control block of VACASK/Ngspice. The ordering is specified by the `order` attribute. If `order` is not set, 0 is assumed. The symbols (blocks) are netlisted in the ascending `order`.
Each block displays only those attributes that are specified (i.e. the string length is>0). Netlisting is triggered by the `command_block.sym` block. In order for the netlister to generate the control block you have to place it in the schematic exactly once. In order for netlisting to work you have to source the `analyses.init.tcl` script at Xschem startup by adding the following line to xschemrc.
```
source analyses.init.tcl
```
An example that demonstrates the capabilities of this library is in file `demo.sch`.
# Setting up sweeps
A sweep is defined with an instance of the `sweep.sym` block. Each sweep has a `name` and a `tag` attribute. The `tag` is the name of the variable that will hold the swept values in the simulator's output file (applies only to VACASK). The `name` of the sweep is the one you have to refer to in an analysis to make sweep that particular analysis. To sweep an analysis set its `sweep` parameter to the `name` of the sweep that applies to that analysis. Each `sweep.sym` instance has a `sweep` parameter. This parameter makes it possible to chain sweeps and form multidimensional sweeps.
For Ngspice sweeps are supported only for the operating point analysis where they are limited to a maximum of 2 dimensions.
# Available analyses
The following analyses are supported
|Symbol |VACASK |Ngspice |
|-----------|----------------|-----------|
|op.sym |op |op |
|dc1d.sym |1D sweep of op |dc (1D) |
|dcinc.sym |dcinc |- |
|dcxf.sym |dcxf |tf |
|ac.sym |ac |ac |
|acxf.sym |acxf |- |
|noise.sym |noise |noise |
|tran.sym |tran |tran |
|hb.sym |hb |- |
# Verbatim blocks
To put verbatim text in a control block the `verbatim.sym` block can be used. The `simulator` attribute specifies the simulator for which the block will be netlisted. If the attribute is not specified the block is netlisted for all simulators. The contents of the block are specified by the `verbatim` attribute.
# Postprocessing scripts
Postprocessing scripts can be invoked with instances of the the `postproc.sym` block. The `tool` attribute specifies the (double-quoted) external program to invoke. The `file` attribute specifies the (double-quoted) name of the file that will be passed to the tool. If unquoted `PYTHON` is specified as the `tool` the `python3` interpreter is invoked under Linux and `python.exe` is invoked under Windows.

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@ -0,0 +1,54 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_ac
template="name=ac1
only_toplevel=false
order=\\"\\"
sweep=\\"\\"
from="10"
to="100k"
step=\\"\\"
mode=\\"\\\\\\"dec\\\\\\"\\"
points=\\"10\\"
values=\\"\\"
nodeset=\\"\\"
store=\\"\\"
write=\\"\\"
writeop=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {AC} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_ac @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

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@ -0,0 +1,56 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_acxf
template="name=acxf1
only_toplevel=false
order=\\"\\"
sweep=\\"\\"
outp=\\"\\\\\\"out\\\\\\"\\"
outn=\\"\\"
from="10"
to="100k"
step=\\"\\"
mode=\\"\\\\\\"dec\\\\\\"\\"
points=\\"10\\"
values=\\"\\"
nodeset=\\"\\"
store=\\"\\"
write=\\"\\"
writeop=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {AC XF} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_acxf @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

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@ -0,0 +1,360 @@
namespace eval ::analyses {
# Parenthesize string if not empty
proc parenthesize {str} {
if {[string length $str] > 0} {
return "( $str )"
} else {
return "$str"
}
}
# Indent a multiline string
proc indent {str indent} {
set lines [split $str \n]
set indented_lines [lmap line $lines {string cat $indent $line}]
return [join $indented_lines \n]
}
# Helper function for display
# props: flat list of name-type pairs
# type can be
# N .. normal, print value
# G .. given, print if parameter is given (not empty string)
# SG .. string given, if quoted, print it out, otherwise just print given
# NV .. normal, value only
proc format_props {symname props} {
set args {}
foreach {propname type} $props {
set val [ xschem getprop instance $symname $propname ]
set len [string len $val]
set quoted [expr {[string index $val 0] eq "\""}]
if {$len > 0} {
if { $type eq "N" } {
lappend args "$propname=$val"
} elseif { $type eq "NV" } {
lappend args "$val"
} elseif { $type eq "G" } {
lappend args "$propname given"
} elseif { $type eq "SG" } {
if {$quoted} {
lappend args "$propname=$val"
} else {
lappend args "$propname given"
}
}
}
}
return [join $args "\n"]
}
# Helper function for spectre netlisting
# N .. normal
# NV .. normal, value only
# S .. string (dump quoted)
proc format_args_spectre {symname props} {
set str ""
set args {}
foreach {propname type} $props {
set val [ xschem getprop instance $symname $propname ]
set len [string len $val]
if {$len > 0} {
set first false
if { $type eq "N" } {
lappend args "$propname=$val"
} elseif { $type eq "NV" } {
lappend args "$val"
} elseif { $type eq "S" } {
lappend args "$propname=\"$val\""
}
}
}
return [join $args " "]
}
# Display output order
proc display_order {symname} {
set names [list order NV]
set txt [format_props $symname $names]
if {[string length $txt] > 0} {
return "#$txt"
} else {
return "unordered (#0)"
}
}
# Display simulator name
proc display_simulator {symname} {
set names [list simulator NV]
return [format_props $symname $names]
}
# Display sweep
proc display_sweep {symname} {
set names [list sweep N instance N model N parameter N "option" N "variable" N from N to N step N mode N points N "values" N continuation N]
return [format_props $symname $names]
}
# Display verbatim block
proc display_verbatim {symname} {
return [format_props $symname [list verbatim NV]]
}
# Display OP analysis
proc display_op {symname} {
set names [list sweep N nodeset SG store N write N]
return [format_props $symname $names]
}
# Display 1D DC sweep analysis
proc display_dc1d {symname} {
set names [list sweep N instance N model N parameter N "option" N "variable" N from N to N step N mode N points N "values" N continuation N nodeset SG store N write N]
return [format_props $symname $names]
}
# Display DCINC analysis
proc display_dcinc {symname} {
set names [list sweep N nodeset SG store N write N writeop N]
return [format_props $symname $names]
}
# Display DCXF analysis
proc display_dcxf {symname} {
set names [list sweep N outp N outn N nodeset SG store N write N writeop N]
return [format_props $symname $names]
}
# Display AC analysis
proc display_ac {symname} {
set names [list sweep N from N to N step N mode N points N values N nodeset SG store N write N writeop N]
return [format_props $symname $names]
}
# Display XF analysis
proc display_acxf {symname} {
set names [list sweep N outp N outn N from N to N step N mode N points N values N nodeset SG store N write N writeop N]
return [format_props $symname $names]
}
# Display NOISE analysis
proc display_noise {symname} {
set names [list sweep N outp N outn N in N from N to N step N mode N points N values N ptssum N nodeset SG store N write N writeop N]
return [format_props $symname $names]
}
# Display TRAN analysis
proc display_tran {symname} {
set names [list sweep N step N stop N start N maxstep N icmode N nodeset SG ic SG store N write N]
return [format_props $symname $names]
}
# Display HB analysis
proc display_hb {symname} {
set names [list sweep N freq N nharm N immax N truncate N samplefac N nper N sample N harmonic N imorder N nodeset N store N write N]
return [format_props $symname $names]
}
# Display postprocessing
proc display_postprocess {symname} {
set names [list file N]
return [format_props $symname $names]
}
# Netlister for spectre
proc netlister {netlist_type} {
set cmds {}
set types [dict create]
set prefix "netlist_command_"
foreach {name symfile type} [xschem instance_list] {
if {[string match netlist_* $type]} {
dict set types $name $type
}
if {[string match $prefix* $type]} {
# Get order
set order [xschem getprop instance $name order]
if {[string len $order] == 0} {
set order 0
}
# Append as sublist
lappend cmds [list $order $name $type]
}
}
# Sort
set cmds [lsort -integer -index 0 $cmds]
# Loop and format
set blocks {}
foreach tuple $cmds {
lassign $tuple order name type
set suffix [string range $type [string length $prefix] end]
# Construct formatter function name
set func [join [list "format_" "$suffix" "_" "$netlist_type"] ""]
try {
set cmd [$func $name]
if {[string length $cmd] > 0} {
lappend blocks [format_sweep_chain_spectre $name $cmd types]
}
} on error (msg) {
puts "Error during formatting command $name"
continue
}
}
set control [indent [join $blocks "\n"] " "]
return [join [list "//// begin user architecture code" "control" "$control" "endc" "//// end user architecture code"] "\n"]
}
# Add sweep chain to analysis (spectre)
proc format_sweep_chain_spectre {name anstr types} {
upvar 1 $types typesdict
set sweep [ xschem getprop instance $name sweep ]
set sweeplist {}
format_sweep_spectre $name sweeplist typesdict
# Do we have any sweeps
if {[llength $sweeplist] > 0} {
# Yes, reverse sweep chain
set sweeplist [lreverse $sweeplist]
# Join sweeps
set sweeps [join [lreverse $sweeplist] "\n"]
return "$sweeps\n $anstr"
} else {
return "$anstr"
}
}
# Sweep formatter (spectre), construct sweep chain, innermost first
proc format_sweep_spectre {parent sweeplist types} {
upvar 1 $sweeplist swl
upvar 1 $types typesdict
set sweep [ xschem getprop instance $parent sweep ]
if {[string length $sweep] > 0} {
# Parent has sweep property
set tag [ xschem getprop instance $sweep tag ]
set type [dict get $typesdict $sweep]
if {[string length $tag] > 0 && ($type eq "netlist_modifier_sweep")} {
# Sweep has tag property
try {
lappend swl [format_single_sweep_spectre $sweep]
} on error (msg) {
# Stop traversing chain on error
puts "Error during formating command $sweep"
return
}
# Recursion into parent sweep
format_sweep_spectre $sweep swl typesdict
}
}
}
# Fomat a single sweep
proc format_single_sweep_spectre {sweep} {
# Parent has sweep property
set tag [ xschem getprop instance $sweep tag ]
return "sweep $tag ( [format_sweep_spectre_params $sweep] [format_sweep_spectre_range $sweep] )"
}
# Sweep formatter (spectre), what to sweep
proc format_sweep_spectre_params {name} {
return [format_args_spectre $name [list instance N model N parameter N "option" N "variable" N]]
}
# Sweep formatter (spectre), how to sweep
proc format_sweep_spectre_range {name} {
return [format_args_spectre $name [list from N to N step N mode N points N "values" N continuation N]]
}
# Analysis formatters, spectre
proc format_verbatim_spectre {name} {
set sim [ xschem getprop instance $name simulator ]
set dump false
if {[string length $sim]==0} {
set dump true
} else {
try {
if {[sim_is_$sim]} {
set dump true
}
} on error (msg) {}
}
if { !$dump } {
return ""
}
return [format_args_spectre $name [list verbatim NV]]
}
proc format_analysis_op_spectre {name} {
set args [format_args_spectre $name [list nodeset N store N write N]]
return "analysis $name op [parenthesize $args]"
}
proc format_analysis_dc1d_spectre {name} {
# OP formatting
set args [format_args_spectre $name [list nodeset N store N write N]]
set anstr "analysis $name op [parenthesize $args]"
# 1D sweep formatting
set swp [format_single_sweep_spectre $name]
return "$swp\n $anstr"
}
proc format_analysis_dcinc_spectre {name} {
set args [format_args_spectre $name [list nodeset N store N write N writeop N]]
return "analysis $name dcinc [parenthesize $args]"
}
proc format_signal_output_spectre {name} {
set outp [ xschem getprop instance $name outp ]
set outn [ xschem getprop instance $name outn ]
set vecstr "\[ $outp"
if {[string length $outn] > 0} {
append vecstr ", $outn"
}
append vecstr " \]"
return $vecstr
}
proc format_analysis_dcxf_spectre {name} {
set args "out=[format_signal_output_spectre $name] "
append args [format_args_spectre $name [list nodeset N store N write N writeop N]]
return "analysis $name dcxf [parenthesize $args]"
}
proc format_analysis_ac_spectre {name} {
set args "[format_sweep_spectre_range $name] "
append args [format_args_spectre $name [list nodeset N store N write N writeop N]]
return "analysis $name ac [parenthesize $args]"
}
proc format_analysis_acxf_spectre {name} {
set args "out=[format_signal_output_spectre $name] "
append args "[format_sweep_spectre_range $name] "
append args [format_args_spectre $name [list nodeset N store N write N writeop N]]
return "analysis $name acxf [parenthesize $args]"
}
proc format_analysis_noise_spectre {name} {
set args "out=[format_signal_output_spectre $name] "
append args "[format_args_spectre $name [list in N]] "
append args "[format_sweep_spectre_range $name] "
append args [format_args_spectre $name [list nodeset N store N write N writeop N]]
return "analysis $name noise [parenthesize $args]"
}
proc format_analysis_tran_spectre {name} {
set args [format_args_spectre $name [list step N stop N start N maxstep N icmode N nodeset N ic N store N write N]]
return "analysis $name tran [parenthesize $args]"
}
proc format_analysis_hb_spectre {name} {
set args [format_args_spectre $name [list freq N nharm N immax N truncate N samplefac N nper N sample N harmonic N imorder N nodeset N store N write N]]
return "analysis $name hb [parenthesize $args]"
}
proc format_postprocess_spectre {name} {
set tool [format_args_spectre $name [list tool NV]]
set file [format_args_spectre $name [list file NV]]
return "postprocess($tool, $file)"
}
# TODO: add x, meg, mil to vacask SI prefixes to VACASK
# TODO: add all VACASK analyses
# TODO: add ngspice formatting
}

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@ -0,0 +1,42 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_header
template="name=CMD
only_toplevel=false
"
format="tcleval([ ::analyses::netlister spice ])"
spectre_format="tcleval([ ::analyses::netlister spectre ])"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {Cmd netlister} 5 -20 0 0 0.3 0.3 {}

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@ -0,0 +1,60 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_dc1d
template="name=dc1
only_toplevel=false
order=\\"\\"
tag=\\"sweep\\"
sweep=\\"\\"
instance=\\"\\\\\\"v1\\\\\\"\\"
model=\\"\\"
parameter=\\"\\"
option=\\"\\"
variable=\\"\\"
from=0
to=0.1
step=0.01
mode=\\"\\"
points=\\"\\"
values=\\"\\"
continuation=\\"\\"
nodeset=\\"\\"
store=\\"\\"
write=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {DC sweep (1D)} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_dc1d @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

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@ -0,0 +1,48 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_dcinc
template="name=dcinc1
only_toplevel=false
order=\\"\\"
sweep=\\"\\"
nodeset=\\"\\"
store=\\"\\"
write=\\"\\"
writeop=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {DC incremental} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_dcinc @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

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@ -0,0 +1,50 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_dcxf
template="name=dcxf1
only_toplevel=false
order=\\"\\"
sweep=\\"\\"
outp=\\"out\\"
outn=\\"\\"
nodeset=\\"\\"
store=\\"\\"
write=\\"\\"
writeop=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {DC XF} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_dcxf @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

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@ -0,0 +1,193 @@
v {xschem version=3.4.8RC file_version=1.3}
G {}
K {}
V {}
S {}
F {}
E {}
C {op.sym} 470 1220 0 0 {name=op1
only_toplevel=false
order="1"
sweep="inner"
nodeset=""
store=""
write=""
}
C {sweep.sym} 290 1220 0 0 {name=inner
only_toplevel=false
tag="vds"
sweep="outer"
instance="\\"vds\\""
model=""
parameter="\\"dc\\""
option=""
variable=""
from=0
to=1.2
step=0.01
mode=""
points=""
values=""
}
C {sweep.sym} 110 1220 0 0 {name=outer
only_toplevel=false
tag="vgs"
sweep=""
instance="\\"vgs\\""
model=""
parameter="\\"dc\\""
option=""
variable=""
from=0
to=1.2
step=0.2
mode=""
points=""
values=""
}
C {tran.sym} 470 1360 0 0 {name=tran1
only_toplevel=false
order="2"
sweep=""
step="1u"
stop="100u"
start=""
maxstep=""
icmode=""
nodeset=""
ic=""
store=""
write=""
}
C {verbatim.sym} 470 1520 0 0 {name=verbatim1
only_toplevel=false
order="3"
simulator="vacask"
verbatim="// A comment
// Another one"
}
C {dc1d.sym} 720 1110 0 0 {name=dc1
only_toplevel=false
order="4"
tag="sweep"
sweep=""
instance="\\"v1\\""
model=""
parameter=""
option=""
variable=""
from=0
to=0.1
step=0.01
mode=""
points=""
values=""
continuation=""
nodeset=""
store=""
write=""
}
C {dcinc.sym} 720 1320 0 0 {name=dcinc1
only_toplevel=false
order="5"
sweep=""
nodeset=""
store=""
write=""
writeop="1"
}
C {dcxf.sym} 720 1460 0 0 {name=dcxf1
only_toplevel=false
order=""
sweep=""
outp="\\"out\\""
outn=""
nodeset=""
store=""
write=""
writeop=""
}
C {ac.sym} 720 1600 0 0 {name=ac1
only_toplevel=false
order="7"
sweep=""
from=10
to=100k
step=""
mode="\\"dec\\""
points="10"
values=""
nodeset="[\\"a\\", 0.5]"
store=""
write=""
writeop=""
}
C {acxf.sym} 960 1100 0 0 {name=acxf1
only_toplevel=false
order="8"
sweep=""
outp="\\"out\\""
outn=""
from=10
to=100k
step=""
mode="\\"dec\\""
points="10"
values=""
nodeset=""
store=""
write=""
writeop=""
}
C {noise.sym} 960 1340 0 0 {name=noise1
only_toplevel=false
order="9"
sweep=""
outp="\\"out\\""
outn=""
in=\\"vin\\"
from=10
to=100k
step=""
mode="\\"dec\\""
points="10"
values=""
ptssum=""
nodeset=""
store=""
write=""
writeop=""
}
C {hb.sym} 960 1590 0 0 {name=hb1
only_toplevel=false
order="10"
sweep=""
freq=[100k]
nharm=10
immax=""
truncate="\\"box\\""
samplefac=""
nper=""
sample=""
harmonic=""
imorder=""
nodeset=""
store=""
write=""
}
C {postproc.sym} 1160 1100 0 0 {name=postproc1
only_toplevel=false
order="12"
tool="PYTHON"
file="\\"script.py\\""
}
C {verbatim.sym} 470 1680 0 0 {name=verbatim2
only_toplevel=false
order="3"
simulator="ngspice"
verbatim="* A comment
* Another one"
}
C {command_block.sym} 470 1110 0 0 {name=CMD
only_toplevel=false
}

View File

@ -0,0 +1,56 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_hb
template="name=hb1
only_toplevel=false
order=\\"\\"
sweep=\\"\\"
freq="[100k]"
nharm="10"
immax=\\"\\"
truncate=\\"\\\\\\"box\\\\\\"\\"
samplefac=\\"\\"
nper=\\"\\"
sample=\\"\\"
harmonic=\\"\\"
imorder=\\"\\"
nodeset=\\"\\"
store=\\"\\"
write=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {HB} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_hb @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

View File

@ -0,0 +1,58 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_noise
template="name=noise1
only_toplevel=false
order=\\"\\"
sweep=\\"\\"
outp=\\"\\\\\\"out\\\\\\"\\"
outn=\\"\\"
in="\\\\\\"vin\\\\\\""
from="10"
to="100k"
step=\\"\\"
mode=\\"\\\\\\"dec\\\\\\"\\"
points=\\"10\\"
values=\\"\\"
ptssum=\\"\\"
nodeset=\\"\\"
store=\\"\\"
write=\\"\\"
writeop=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {Noise} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_noise @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

View File

@ -0,0 +1,47 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_op
template="name=op1
only_toplevel=false
order=\\"\\"
sweep=\\"\\"
nodeset=\\"\\"
store=\\"\\"
write=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {Operating point} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_op @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

View File

@ -0,0 +1,45 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_postprocess
template="name=postproc1
only_toplevel=false
order=\\"\\"
tool=\\"PYTHON\\"
file=\\"\\\\\\"script.py\\\\\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {@tool} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_postprocess @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

View File

@ -0,0 +1,56 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_modifier_sweep
template="name=sweep
only_toplevel=false
tag=\\"sweep\\"
sweep=\\"\\"
instance=\\"\\\\\\"v1\\\\\\"\\"
model=\\"\\"
parameter=\\"\\"
option=\\"\\"
variable=\\"\\"
from=0
to=0.1
step=0.01
mode=\\"\\"
points=\\"\\"
values=\\"\\"
continuation=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {Sweep} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_sweep @name ])} 5 50 0 0 0.3 0.3 {}
T {@tag} 5 0 0 0 0.3 0.3 {}

View File

@ -0,0 +1,53 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_analysis_tran
template="name=tran1
only_toplevel=false
order=\\"\\"
sweep=\\"\\"
step=\\"1u\\"
stop=\\"100u\\"
start=\\"\\"
maxstep=\\"\\"
icmode=\\"\\"
nodeset=\\"\\"
ic=\\"\\"
store=\\"\\"
write=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {Transient} 5 -20 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_tran @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}

View File

@ -0,0 +1,45 @@
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=netlist_command_verbatim
template="name=verbatim1
only_toplevel=false
order=\\"\\"
simulator=\\"spectre\\"
verbatim=\\"\\"
"}
V {}
S {}
F {}
E {}
L 4 0 -30 140 -30 {}
L 4 0 -30 0 30 {}
L 4 140 -30 140 30 {}
L 4 0 30 140 30 {}
L 4 10 40 150 40 {}
L 4 150 -10 150 40 {}
L 4 10 30 10 40 {}
L 4 140 -10 150 -10 {}
T {@name} 5 -50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_verbatim @name ])} 5 50 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_order @name ])} 5 0 0 0 0.3 0.3 {}
T {tcleval([ ::analyses::display_simulator @name ])} 5 -20 0 0 0.3 0.3 {}

View File

@ -0,0 +1,8 @@
set netlist_dir $env(HOME)/.xschem/simulations
set netlist_type spectre
set editor {kwrite}
set netlist_type spectre
set netlist_show 1
source analyses.init.tcl