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when doing spice netlisting if top level has a symbol (and the symbol has i/o ports) use the symbol for printing the top level subckt port list. This ensures same port ordering when netlisting a testbench containing a component and netlisting the component itself. Tab context menu: open Symbol / open Schematic will use the search_schematic setting and search counterpart accordingly.

This commit is contained in:
stefan schippers 2023-11-16 01:26:55 +01:00
parent 5117001a9c
commit a50bfb3622
5 changed files with 60 additions and 69 deletions
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40
src/spice_netlist.c
View File

@ -245,6 +245,9 @@ int global_spice_netlist(int global) /* netlister driver */
Str_hashentry *model_entry; Str_hashentry *model_entry;
int lvs_ignore = tclgetboolvar("lvs_ignore"); int lvs_ignore = tclgetboolvar("lvs_ignore");
int save_prev_mod = xctx->prev_set_modify; int save_prev_mod = xctx->prev_set_modify;
struct stat buf;
char *top_symbol_name = NULL;
int found_top_symbol = 0; /* if top level has a symbol use it for pin ordering */
split_f = tclgetboolvar("split_files"); split_f = tclgetboolvar("split_files");
dbg(1, "global_spice_netlist(): invoking push_undo()\n"); dbg(1, "global_spice_netlist(): invoking push_undo()\n");
@ -310,20 +313,29 @@ int global_spice_netlist(int global) /* netlister driver */
fprintf(fd,".subckt %s", get_cell(xctx->sch[xctx->currsch], 0)); fprintf(fd,".subckt %s", get_cell(xctx->sch[xctx->currsch], 0));
/* print top subckt ipin/opins */ /* print top subckt ipin/opins */
for(i=0;i<xctx->instances; ++i) { my_strdup2(_ALLOC_ID_, &top_symbol_name, abs_sym_path(add_ext(xctx->current_name, ".sym"), ""));
if(skip_instance(i, 1, lvs_ignore)) continue; if(!stat(top_symbol_name, &buf)) { /* if top level has a symbol use the symbol for pin ordering */
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type); dbg(1, "found top level symbol %s\n", top_symbol_name);
dbg(1, "global_spice_netlist(): |%s|\n", type); load_sym_def(top_symbol_name, NULL);
/* /* only use the symbol if it has pins */
if( type && !strcmp(type,"netlist_options") ) { if(xctx->sym[xctx->symbols - 1].rects[PINLAYER] > 0) {
continue; fprintf(fd," ");
} print_spice_subckt_nodes(fd, xctx->symbols - 1);
*/ found_top_symbol = 1;
if( type && IS_PIN(type)) { }
str_tmp = expandlabel ( (xctx->inst[i].lab ? xctx->inst[i].lab : ""), &multip); remove_symbol(xctx->symbols - 1);
/*must handle invalid node names */ my_free(_ALLOC_ID_, &top_symbol_name);
fprintf(fd, " %s", str_tmp ? str_tmp : "(NULL)" ); }
} if(!found_top_symbol) {
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type)) {
str_tmp = expandlabel ( (xctx->inst[i].lab ? xctx->inst[i].lab : ""), &multip);
/*must handle invalid node names */
fprintf(fd, " %s", str_tmp ? str_tmp : "(NULL)" );
}
}
} }
fprintf(fd,"\n"); fprintf(fd,"\n");

14
src/xschem.tcl
View File

@ -5897,7 +5897,7 @@ proc tab_ctx_cmd {tab_but what} {
# puts $filename # puts $filename
} }
proc tab_context_menu {tab_but} { proc tab_context_menu {tab_but} {
global retval global retval search_schematic
# find filename associated with tab button # find filename associated with tab button
@ -5917,11 +5917,19 @@ proc tab_context_menu {tab_but} {
xschem new_schematic switch $old {} 0 ;# no draw xschem new_schematic switch $old {} 0 ;# no draw
if {$filetype ne {symbol}} { if {$filetype ne {symbol}} {
set counterpart [abs_sym_path $filename .sym] if {$search_schematic == 1} {
set counterpart [abs_sym_path [xschem get current_name] {.sym}]
} else {
set counterpart [abs_sym_path $filename .sym]
}
set msg {Open symbol} set msg {Open symbol}
set img CtxmenuSymbol set img CtxmenuSymbol
} else { } else {
set counterpart [abs_sym_path $filename .sch] if {$search_schematic == 1} {
set counterpart [abs_sym_path [xschem get current_name] {.sch}]
} else {
set counterpart [abs_sym_path $filename .sch]
}
set msg {Open schematic} set msg {Open schematic}
set img CtxmenuSchematic set img CtxmenuSchematic
} }

2
tests/xschemtest.tcl
View File

@ -197,7 +197,7 @@ proc netlist_test {} {
inst_sch_select.sch spice 801962545 inst_sch_select.sch spice 801962545
test_bus_tap.sch spice 181420586 test_bus_tap.sch spice 181420586
loading.sch vhdl 2975204502 loading.sch vhdl 2975204502
mos_power_ampli.sch spice 2027301758 mos_power_ampli.sch spice 4084823731
hierarchical_tedax.sch tedax 998070173 hierarchical_tedax.sch tedax 998070173
LCC_instances.sch spice 696885230 LCC_instances.sch spice 696885230
pcb_test1.sch tedax 1925087189 pcb_test1.sch tedax 1925087189

24
xschem_library/examples/mos_power_ampli.sch
View File

@ -137,11 +137,11 @@ N 690 -1210 690 -970 {lab=VBOOST}
N 690 -910 690 -900 {lab=B1} N 690 -910 690 -900 {lab=B1}
N 260 -550 260 -540 {lab=E9} N 260 -550 260 -540 {lab=E9}
N 150 -180 260 -180 {lab=VSS} N 150 -180 260 -180 {lab=VSS}
N 40 -300 220 -300 {lab=B3} N 50 -300 220 -300 {lab=B3}
N 260 -270 260 -240 {lab=E3} N 260 -270 260 -240 {lab=E3}
N 150 -240 150 -180 {lab=VSS} N 150 -240 150 -180 {lab=VSS}
N 40 -210 40 -180 {lab=VSS} N 50 -240 50 -180 {lab=VSS}
N 40 -180 150 -180 {lab=VSS} N 50 -180 150 -180 {lab=VSS}
N 690 -690 1110 -690 {lab=OUTI} N 690 -690 1110 -690 {lab=OUTI}
N 180 -550 260 -550 {lab=E9} N 180 -550 260 -550 {lab=E9}
N 1110 -700 1110 -690 {lab=OUTI} N 1110 -700 1110 -690 {lab=OUTI}
@ -153,6 +153,7 @@ N 1110 -820 1110 -790 {lab=SA}
N 860 -850 1070 -850 {lab=GA} N 860 -850 1070 -850 {lab=GA}
N 340 -830 340 -780 {lab=C2} N 340 -830 340 -780 {lab=C2}
N 340 -720 340 -650 {lab=C9} N 340 -720 340 -650 {lab=C9}
N 220 -720 340 -720 {lab=C9}
N 180 -690 180 -650 {lab=C5} N 180 -690 180 -650 {lab=C5}
N 1330 -680 1390 -680 {lab=OUT} N 1330 -680 1390 -680 {lab=OUT}
N 1110 -680 1240 -680 {lab=OUTI} N 1110 -680 1240 -680 {lab=OUTI}
@ -183,7 +184,7 @@ N 340 -1270 560 -1270 {lab=VPP}
N 1110 -1270 1110 -880 { lab=VPP} N 1110 -1270 1110 -880 { lab=VPP}
N 560 -1270 1110 -1270 {lab=VPP} N 560 -1270 1110 -1270 {lab=VPP}
N 230 -1040 800 -1040 { lab=#net2} N 230 -1040 800 -1040 { lab=#net2}
N 0 -180 40 -180 { N 0 -180 50 -180 {
lab=VSS} lab=VSS}
N 0 -140 1110 -140 { N 0 -140 1110 -140 {
lab=VNN} lab=VNN}
@ -196,14 +197,6 @@ N 400 -620 400 -570 {
lab=MINUS} lab=MINUS}
N 380 -620 400 -620 { N 380 -620 400 -620 {
lab=MINUS} lab=MINUS}
N 300 -720 340 -720 {
lab=C9}
N 220 -720 240 -720 {
lab=#net8}
N 40 -300 40 -270 {
lab=B3}
N 150 -400 150 -360 {
lab=VPP}
C {ipin.sym} 0 -620 0 0 {name=p0 lab=PLUS} C {ipin.sym} 0 -620 0 0 {name=p0 lab=PLUS}
C {ipin.sym} 0 -140 0 0 {name=p3 lab=VNN} C {ipin.sym} 0 -140 0 0 {name=p3 lab=VNN}
C {nmos3.sym} 1090 -530 0 0 {name=xm2 model=irf540 m=1 C {nmos3.sym} 1090 -530 0 0 {name=xm2 model=irf540 m=1
@ -294,9 +287,9 @@ url="http://www.futurlec.com/Datasheet/Diodes/1N746-1N759.pdf"
net_name=true} net_name=true}
C {npn.sym} 240 -300 0 0 {name=Q3 model=q2n2222 area=1 net_name=true} C {npn.sym} 240 -300 0 0 {name=Q3 model=q2n2222 area=1 net_name=true}
C {res.sym} 150 -330 0 1 {name=R1 m=1 value=10k net_name=true} C {res.sym} 150 -330 0 1 {name=R1 m=1 value=10k net_name=true}
C {lab_pin.sym} 150 -400 0 0 {name=p7 lab=VPP} C {lab_pin.sym} 150 -360 0 0 {name=p7 lab=VPP}
C {res.sym} 260 -210 0 1 {name=R10 m=1 value=170 net_name=true} C {res.sym} 260 -210 0 1 {name=R10 m=1 value=170 net_name=true}
C {capa.sym} 40 -240 0 0 {name=C3 m=1 value=100n net_name=true} C {capa.sym} 50 -270 0 0 {name=C3 m=1 value=100n net_name=true}
C {res.sym} 560 -700 0 1 {name=R12 m=1 value=1300 net_name=true} C {res.sym} 560 -700 0 1 {name=R12 m=1 value=1300 net_name=true}
C {lab_pin.sym} 690 -890 0 0 {name=p12 lab=B1} C {lab_pin.sym} 690 -890 0 0 {name=p12 lab=B1}
C {lab_pin.sym} 340 -550 0 1 {name=p13 lab=E9} C {lab_pin.sym} 340 -550 0 1 {name=p13 lab=E9}
@ -305,7 +298,7 @@ C {lab_pin.sym} 560 -650 0 1 {name=p20 lab=E8}
C {lab_pin.sym} 840 -940 0 0 {name=p21 lab=E11} C {lab_pin.sym} 840 -940 0 0 {name=p21 lab=E11}
C {lab_pin.sym} 260 -260 0 1 {name=p22 lab=E3} C {lab_pin.sym} 260 -260 0 1 {name=p22 lab=E3}
C {lab_pin.sym} 260 -350 0 0 {name=p26 lab=C3} C {lab_pin.sym} 260 -350 0 0 {name=p26 lab=C3}
C {lab_pin.sym} 40 -300 0 0 {name=p30 lab=B3} C {lab_pin.sym} 50 -300 0 0 {name=p30 lab=B3}
C {lab_pin.sym} 520 -580 0 0 {name=p33 lab=VSS} C {lab_pin.sym} 520 -580 0 0 {name=p33 lab=VSS}
C {res.sym} 340 -750 0 1 {name=R13 m=1 value=300 net_name=true} C {res.sym} 340 -750 0 1 {name=R13 m=1 value=300 net_name=true}
C {npn.sym} 200 -720 0 1 {name=Q7 model=q2n2222 area=1 net_name=true} C {npn.sym} 200 -720 0 1 {name=Q7 model=q2n2222 area=1 net_name=true}
@ -472,4 +465,3 @@ C {ngspice_get_expr.sym} 1130 -860 0 0 {name=r22
node="[ngspice::get_current \{xm1.rd[i]\}]" node="[ngspice::get_current \{xm1.rd[i]\}]"
descr = current descr = current
} }
C {ammeter.sym} 270 -720 1 0 {name=v9 net_name=true }

49
xschem_library/examples/poweramp.sch
View File

@ -38,8 +38,8 @@ B 2 1200 -500 1880 -310 {flags=graph
y1 = -0.0059 y1 = -0.0059
y2 = 11 y2 = 11
divy = 6 divy = 6
x1=0.0228839 x1=0.00562909
x2=0.0242439 x2=0.0165959
divx=10 divx=10
node="i(v.x1.vu) node="i(v.x1.vu)
i(v.x0.vu) i(v.x0.vu)
@ -52,8 +52,8 @@ B 2 1200 -830 1880 -520 {flags=graph
y1 = -49 y1 = -49
y2 = 58 y2 = 58
divy = 12 divy = 12
x1=0.0228839 x1=0.00562909
x2=0.0242439 x2=0.0165959
divx=10 divx=10
node="outp node="outp
outm outm
@ -68,8 +68,8 @@ B 2 1200 -1020 1880 -830 {flags=graph
y1 = 0 y1 = 0
y2 = 830 y2 = 830
divy = 6 divy = 6
x1=0.0228839 x1=0.00562909
x2=0.0242439 x2=0.0165959
divx=10 divx=10
@ -82,8 +82,8 @@ B 2 1200 -310 1880 -120 {flags=graph
y1 = 0 y1 = 0
y2 = 840 y2 = 840
divy = 6 divy = 6
x1=0.0228839 x1=0.00562909
x2=0.0242439 x2=0.0165959
divx=10 divx=10
@ -185,8 +185,8 @@ N 240 -320 240 -220 { lab=INX}
N 160 -1220 180 -1220 {lab=#net3} N 160 -1220 180 -1220 {lab=#net3}
N 160 -1060 180 -1060 {lab=#net4} N 160 -1060 180 -1060 {lab=#net4}
N 70 -1140 180 -1140 {lab=#net5} N 70 -1140 180 -1140 {lab=#net5}
C {vsource.sym} 70 -1170 0 0 {name=V1 value="dc \{VPP\} pwl 0 0 1m \{VPP\}"} C {vsource.sym} 70 -1170 0 0 {name=V1 value="dc 50 pwl 0 0 1m 50"}
C {vsource.sym} 70 -1110 0 0 {name=V0 value="dc \{VPP\} pwl 0 0 1m \{VPP\}"} C {vsource.sym} 70 -1110 0 0 {name=V0 value="dc 50 pwl 0 0 1m 50"}
C {lab_pin.sym} 310 -1220 0 1 {name=p5 lab=VPP} C {lab_pin.sym} 310 -1220 0 1 {name=p5 lab=VPP}
C {lab_pin.sym} 310 -1060 0 1 {name=p6 lab=VNN} C {lab_pin.sym} 310 -1060 0 1 {name=p6 lab=VNN}
C {lab_pin.sym} 310 -1140 0 1 {name=p3 lab=VSS} C {lab_pin.sym} 310 -1140 0 1 {name=p3 lab=VSS}
@ -230,7 +230,7 @@ C {res.sym} 550 -460 0 1 {name=R2 m=1 value='100k'}
C {res.sym} 550 -400 0 1 {name=R3 m=1 value="'100k/(gain-2)'"} C {res.sym} 550 -400 0 1 {name=R3 m=1 value="'100k/(gain-2)'"}
C {vsource.sym} 870 -1140 0 0 {name=V3 C {vsource.sym} 870 -1140 0 0 {name=V3
xvalue="dc 0 pulse -.1 .1 1m .1u .1u 10.1u 20u" xvalue="dc 0 pulse -.1 .1 1m .1u .1u 10.1u 20u"
value="dc 0 sin 0 0.5 \{frequ\} 1m" value="dc 0 sin 0 1 \{frequ\} 1m"
} }
C {res.sym} 240 -810 0 1 {name=R4 m=1 value=100k} C {res.sym} 240 -810 0 1 {name=R4 m=1 value=100k}
C {lab_pin.sym} 240 -860 0 0 {name=p18 lab=VPP} C {lab_pin.sym} 240 -860 0 0 {name=p18 lab=VPP}
@ -338,8 +338,7 @@ spice_ignore=0
value=" value="
.option ITL4=20000 ITL5=0 .option ITL4=20000 ITL5=0
vvss vss 0 dc 0 vvss vss 0 dc 0
.temp 27 .temp 30
.param VPP=50
.param frequ=5k .param frequ=5k
.param gain=45 .param gain=45
.option savecurrents .option savecurrents
@ -352,30 +351,13 @@ vvss vss 0 dc 0
save all save all
op op
write poweramp_op.raw write poweramp_op.raw
tran 8e-7 0.025 uic tran 8e-7 0.07 uic
* .FOUR 20k v(outm,outp) * .FOUR 20k v(outm,outp)
* .probe i(*) * .probe i(*)
plot outp outm
save p(r*) p(v*) save p(r*) p(v*)
write poweramp.raw write poweramp.raw
alterparam VPP=30
reset
save all
op
write poweramp_op2.raw
tran 8e-7 0.025 uic
* .FOUR 20k v(outm,outp)
* .probe i(*)
save p(r*) p(v*)
write poweramp2.raw
quit 0 quit 0
.endc .endc
"} "}
C {simulator_commands.sym} 1020 -870 0 0 {name=COMMANDS1 C {simulator_commands.sym} 1020 -870 0 0 {name=COMMANDS1
@ -441,6 +423,3 @@ simswap
" "
} }
C {launcher.sym} 1000 -220 0 0 {name=h8
descr="Backannotate2"
tclcommand="xschem annotate_op $netlist_dir/poweramp_op2.raw"}