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verilog_ignore, spice_ignore, vhdl_ignore attributes on schematic pins are propagated to symbol pin attributes (if using make symbol from schematic, otherwise propagate by hand). These pins are not netlisted in the respective netlist format

This commit is contained in:
Stefan Schippers 2020-09-02 12:30:52 +02:00
parent fa9bdd44bc
commit 9f82cf47aa
6 changed files with 197 additions and 150 deletions
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36
src/make_sym.awk
View File

@ -91,6 +91,7 @@ function beginfile(f)
index_pin[n_pin] = n_pin # one level indirection for sorting pins 20140519
value_pin[n_pin]=value
label_pin[n_pin] = pin_label
props_pin[n_pin] = rest_of_props()
n_pin++
ip++
}
@ -105,6 +106,7 @@ function beginfile(f)
index_pin[n_pin] = n_pin # one level indirection 20140519
value_pin[n_pin]=value
label_pin[n_pin] = pin_label
props_pin[n_pin] = rest_of_props()
n_pin++
ip++
}
@ -119,6 +121,7 @@ $0 ~ /^C \{.*opin(\.sym)?\}/ && $0 !~ /^C \{.*iopin(\.sym)?\}/ {
index_pin[n_pin] = n_pin # one level indirection 20140519
value_pin[n_pin]=value
label_pin[n_pin] = pin_label
props_pin[n_pin] = rest_of_props()
n_pin++
op++
}
@ -134,11 +137,22 @@ $0 ~ /^C \{.*opin(\.sym)?\}/ && $0 !~ /^C \{.*iopin(\.sym)?\}/ {
index_pin[n_pin] = n_pin # one level indirection 20140519
value_pin[n_pin]=value
label_pin[n_pin] = pin_label
props_pin[n_pin] = rest_of_props()
n_pin++
op++
}
function rest_of_props()
{
sub(/^C \{[^}]+\}.*\{/,"")
sub(/\}[ \t]*$/, "")
sub(/verilog_type[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
sub(/sig_type[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
sub(/lab[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
sub(/value[ \t]*=[ \t]*[^ \t]+[ \t]?/, "")
sub(/^[ \t]*$/, "")
return $0
}
function process_line()
{
@ -245,8 +259,9 @@ function endfile(f) {
{
printf "B 3 " (x-size) " " (y+num_i*space-size) " " (x+size) " " (y+num_i*space+size) \
" {name=" label_pin[i] " generic_type=" sig_type " " >sym
if(value !="") printf "value=" value "}\n" >sym
else printf "}\n" >sym
if(value !="") printf "value=" value " " >sym
printf props_pin[i] > sym
printf "}\n" >sym
print "L 4 " x,y+num_i*space,x+lwidth, y+num_i*space,"{}" >sym
print "T {" label_pin[i] "}",x+lwidth+textdist,y+num_i*space-lab_voffset,0,0,labsize, labsize, "{}" >sym
num_i++ # 20140519
@ -255,8 +270,9 @@ function endfile(f) {
{
printf "B 5 " (x-size) " " (y+num_i*space-size) " " (x+size) " " (y+num_i*space+size) \
" {name=" label_pin[i] vhdt vert " dir=in " >sym
if(value !="") printf "value=" value "}\n" >sym
else printf "}\n" >sym
if(value !="") printf "value=" value " " >sym
printf props_pin[i] > sym
printf "}\n" >sym
print "L 4 " x,y+num_i*space,x+lwidth, y+num_i*space,"{}" >sym
print "T {" label_pin[i] "}",x+lwidth+textdist,y+num_i*space-lab_voffset,0,0,labsize, labsize, "{}" >sym
num_i++ # 20140519
@ -265,8 +281,9 @@ function endfile(f) {
{
printf "B 5 " (-x-size) " " (y+num_o*space-size) " " (-x+size) " " (y+num_o*space+size) \
" {name=" label_pin[i] vhdt vert " dir=out " >sym
if(value !="") printf "value=" value "}\n" >sym
else printf "}\n" >sym
if(value !="") printf "value=" value " " >sym
printf props_pin[i] > sym
printf "}\n" >sym
print "L 4 " (-x-lwidth),(y+num_o*space),-x, (y+num_o*space),"{}" >sym
print "T {" label_pin[i] "}",-x-lwidth-textdist,y+num_o*space-lab_voffset,0,1,labsize, labsize, "{}" >sym
num_o++ # 20140519
@ -275,8 +292,9 @@ function endfile(f) {
{
printf "B 5 " (-x-size) " " (y+num_o*space-size) " " (-x+size) " " (y+num_o*space+size) \
" {name=" label_pin[i] vhdt vert " dir=inout " >sym
if(value !="") printf "value=" value "}\n" >sym
else printf "}\n" >sym
if(value !="") printf "value=" value " " >sym
printf props_pin[i] > sym
printf "}\n" >sym
print "L 7 " (-x-lwidth),(y+num_o*space),-x, (y+num_o*space),"{}" >sym
print "T {" label_pin[i] "}",-x-lwidth-textdist,y+num_o*space-lab_voffset,0,1,labsize, labsize, "{}" >sym
num_o++ # 20140519

125
src/token.c
View File

@ -1118,13 +1118,15 @@ void print_vhdl_element(FILE *fd, int inst) /* 20071217 */
tmp=0;
for(i=0;i<no_of_pins;i++)
{
if( (str_ptr = pin_node(inst,i, &mult, 0)) )
{
if(tmp) fprintf(fd, " ,\n");
fprintf(fd, " %s => %s",
get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"name",0),
str_ptr);
tmp=1;
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
if( (str_ptr = pin_node(inst,i, &mult, 0)) )
{
if(tmp) fprintf(fd, " ,\n");
fprintf(fd, " %s => %s",
get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"name",0),
str_ptr);
tmp=1;
}
}
}
fprintf(fd, "\n);\n\n");
@ -1413,21 +1415,30 @@ void print_spice_subckt(FILE *fd, int symbol)
else if(strcmp(token, "@pinlist")==0) {
for(i=0;i<no_of_pins;i++)
{
str_ptr=
expandlabel(get_tok_value(instdef[symbol].boxptr[PINLAYER][i].prop_ptr,"name",0), &mult);
fprintf(fd, "%s ", str_ptr);
if(strcmp(get_tok_value(instdef[symbol].boxptr[PINLAYER][i].prop_ptr,"spice_ignore",0), "true")) {
str_ptr=
expandlabel(get_tok_value(instdef[symbol].boxptr[PINLAYER][i].prop_ptr,"name",0), &mult);
fprintf(fd, "%s ", str_ptr);
}
}
}
else if(token[0]=='@' && token[1]=='@') { /* recognize single pins 15112003 */
fprintf(fd, "%s ", expandlabel(token+2, &mult));
for(i = 0; i<no_of_pins; i++) {
if(!strcmp(get_tok_value(instdef[symbol].boxptr[PINLAYER][i].prop_ptr,"name",0), token + 2)) break;
}
if(i<no_of_pins && strcmp(get_tok_value(instdef[symbol].boxptr[PINLAYER][i].prop_ptr,"spice_ignore",0), "true")) {
fprintf(fd, "%s ", expandlabel(token+2, &mult));
}
}
/* reference by pin number instead of pin name, allows faster lookup of the attached net name 20180911 */
else if(token[0]=='@' && token[1]=='#') {
pin_number = atoi(token+2);
if(pin_number < no_of_pins) {
str_ptr = get_tok_value(instdef[symbol].boxptr[PINLAYER][pin_number].prop_ptr,"name",0);
fprintf(fd, "%s ", expandlabel(str_ptr, &mult));
pin_number = atoi(token+2);
if(pin_number < no_of_pins) {
if(strcmp(get_tok_value(instdef[symbol].boxptr[PINLAYER][pin_number].prop_ptr,"spice_ignore",0), "true")) {
str_ptr = get_tok_value(instdef[symbol].boxptr[PINLAYER][pin_number].prop_ptr,"name",0);
fprintf(fd, "%s ", expandlabel(str_ptr, &mult));
}
}
}
if(c != '@' && c!='\0' && (c!='\\' || escape) ) fputc(c,fd);
if(c == '@') s--;
@ -1555,9 +1566,11 @@ void print_spice_element(FILE *fd, int inst)
{ /* and node number: m1 n1 m2 n2 .... */
for(i=0;i<no_of_pins;i++)
{
str_ptr = pin_node(inst,i, &mult, 0);
/* fprintf(errfp, "inst: %s --> %s\n", name, str_ptr); */
fprintf(fd, "@%d %s ", mult, str_ptr);
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"spice_ignore",0), "true")) {
str_ptr = pin_node(inst,i, &mult, 0);
/* fprintf(errfp, "inst: %s --> %s\n", name, str_ptr); */
fprintf(fd, "@%d %s ", mult, str_ptr);
}
}
}
else if(token[0]=='@' && token[1]=='@') { /* recognize single pins 15112003 */
@ -1565,8 +1578,10 @@ void print_spice_element(FILE *fd, int inst)
if (!strcmp(
get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"name",0),
token+2)) {
str_ptr = pin_node(inst,i, &mult, 0);
fprintf(fd, "@%d %s", mult, str_ptr);
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"spice_ignore",0), "true")) {
str_ptr = pin_node(inst,i, &mult, 0);
fprintf(fd, "@%d %s", mult, str_ptr);
}
break; /* 20171029 */
}
}
@ -1575,8 +1590,10 @@ void print_spice_element(FILE *fd, int inst)
else if (token[0]=='@' && token[1]=='#') {
pin_number = atoi(token+2);
if (pin_number < no_of_pins) {
str_ptr = pin_node(inst,pin_number, &mult, 0);
fprintf(fd, "@%d %s ", mult, str_ptr);
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][pin_number].prop_ptr,"spice_ignore",0), "true")) {
str_ptr = pin_node(inst,pin_number, &mult, 0);
fprintf(fd, "@%d %s ", mult, str_ptr);
}
}
}
else if (!strncmp(token,"@tcleval", 8)) { /* 20171029 */
@ -2013,14 +2030,15 @@ void print_verilog_element(FILE *fd, int inst)
tmp=0;
for(i=0;i<no_of_pins;i++)
{
if( (str_ptr = pin_node(inst,i, &mult, 0)) )
{
/*printf("print_verilog_element(): expandlabel: str=%s mult=%d\n", str_ptr, mult); */
if(tmp) fprintf(fd,"\n");
fprintf(fd, " @%d %s %s ", mult,
get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"name",0),
str_ptr);
tmp=1;
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
if( (str_ptr = pin_node(inst,i, &mult, 0)) )
{
if(tmp) fprintf(fd,"\n");
fprintf(fd, " @%d %s %s ", mult,
get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"name",0),
str_ptr);
tmp=1;
}
}
}
fprintf(fd, "\n);\n\n");
@ -2185,9 +2203,10 @@ void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 20071217 *
{ /* and node number: m1 n1 m2 n2 .... */
for(i=0;i<no_of_pins;i++)
{
str_ptr = pin_node(inst,i, &mult, 0);
/*fprintf(fd, "@%d %s ", mult, str_ptr); */ /* 25122004 disabled bus handling, until verilog.awk knows about it */
fprintf(fd, "----pin(%s) ", str_ptr);
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
str_ptr = pin_node(inst,i, &mult, 0);
fprintf(fd, "----pin(%s) ", str_ptr);
}
}
}
else if(token[0]=='@' && token[1]=='@') { /* recognize single pins 15112003 */
@ -2195,11 +2214,11 @@ void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 20071217 *
if(!strcmp(
get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"name",0),
token+2
)
) {
str_ptr = pin_node(inst,i, &mult, 0);
/*fprintf(fd, "@%d %s ", mult, str_ptr); */ /* 25122004 disabled bus handling, until verilog.awk knows about it */
fprintf(fd, "----pin(%s) ", str_ptr);
)) {
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
str_ptr = pin_node(inst,i, &mult, 0);
fprintf(fd, "----pin(%s) ", str_ptr);
}
break; /* 20171029 */
}
}
@ -2208,8 +2227,10 @@ void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 20071217 *
else if(token[0]=='@' && token[1]=='#') {
pin_number = atoi(token+2);
if(pin_number < no_of_pins) {
str_ptr = pin_node(inst,pin_number, &mult, 0);
fprintf(fd, "----pin(%s) ", str_ptr);
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][pin_number].prop_ptr,"vhdl_ignore",0), "true")) {
str_ptr = pin_node(inst,pin_number, &mult, 0);
fprintf(fd, "----pin(%s) ", str_ptr);
}
}
}
else if(!strncmp(token,"@tcleval", 8)) { /* 20171029 */
@ -2351,21 +2372,21 @@ void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level primiti
{ /* and node number: m1 n1 m2 n2 .... */
for(i=0;i<no_of_pins;i++)
{
str_ptr = pin_node(inst,i, &mult, 0);
/*fprintf(fd, "@%d %s ", mult, str_ptr); */ /* 25122004 disabled bus handling, until verilog.awk knows about it */
fprintf(fd, "----pin(%s) ", str_ptr);
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
str_ptr = pin_node(inst,i, &mult, 0);
fprintf(fd, "----pin(%s) ", str_ptr);
}
}
}
else if(token[0]=='@' && token[1]=='@') { /* recognize single pins 15112003 */
for(i=0;i<no_of_pins;i++) {
if(!strcmp(
get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"name",0),
token+2
)
) {
str_ptr = pin_node(inst,i, &mult, 0);
/*fprintf(fd, "@%d %s ", mult, str_ptr); */ /* 25122004 disabled bus handling, until verilog.awk knows about it */
fprintf(fd, "----pin(%s) ", str_ptr);
token+2)) {
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
str_ptr = pin_node(inst,i, &mult, 0);
fprintf(fd, "----pin(%s) ", str_ptr);
}
break; /* 20171029 */
}
}
@ -2374,8 +2395,10 @@ void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level primiti
else if(token[0]=='@' && token[1]=='#') {
pin_number = atoi(token+2);
if(pin_number < no_of_pins) {
str_ptr = pin_node(inst,pin_number, &mult, 0);
fprintf(fd, "----pin(%s) ", str_ptr);
if(strcmp(get_tok_value((inst_ptr[inst].ptr+instdef)->boxptr[PINLAYER][pin_number].prop_ptr,"verilog_ignore",0), "true")) {
str_ptr = pin_node(inst,pin_number, &mult, 0);
fprintf(fd, "----pin(%s) ", str_ptr);
}
}
}
else if(!strncmp(token,"@tcleval", 8)) { /* 20171029 */

54
src/verilog_netlist.c
View File

@ -414,12 +414,12 @@ void verilog_block_netlist(FILE *fd, int i) /*20081205 */
tmp=0;
for(j=0;j<instdef[i].rects[PINLAYER];j++)
{
my_strdup(562, &port_value, get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"value",2) );
str_tmp = get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"name",0);
if(tmp) fprintf(fd, " ,\n");
tmp++;
fprintf(fd," %s", str_tmp ? str_tmp : "<NULL>");
if(strcmp(get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
str_tmp = get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"name",0);
if(tmp) fprintf(fd, " ,\n");
tmp++;
fprintf(fd," %s", str_tmp ? str_tmp : "<NULL>");
}
}
fprintf(fd, "\n);\n");
@ -435,26 +435,28 @@ void verilog_block_netlist(FILE *fd, int i) /*20081205 */
tmp=0;
for(j=0;j<instdef[i].rects[PINLAYER];j++)
{
my_strdup(564, &sig_type,get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"verilog_type",0));
my_strdup(565, &port_value, get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"value",2) );
my_strdup(566, &dir_tmp, get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"dir",0) );
if(strcmp(dir_tmp,"in")){
if(!sig_type || sig_type[0]=='\0') my_strdup(567, &sig_type,"wire"); /* 20070720 changed reg to wire */
} else {
if(!sig_type || sig_type[0]=='\0') my_strdup(568, &sig_type,"wire");
if(strcmp(get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
my_strdup(564, &sig_type,get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"verilog_type",0));
my_strdup(565, &port_value, get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"value",2) );
my_strdup(566, &dir_tmp, get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"dir",0) );
if(strcmp(dir_tmp,"in")){
if(!sig_type || sig_type[0]=='\0') my_strdup(567, &sig_type,"wire"); /* 20070720 changed reg to wire */
} else {
if(!sig_type || sig_type[0]=='\0') my_strdup(568, &sig_type,"wire");
}
str_tmp = get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"name",0);
fprintf(fd," %s %s ;\n",
strcmp(dir_tmp,"in")? ( strcmp(dir_tmp,"out")? "inout" :"output" ) : "input",
str_tmp ? str_tmp : "<NULL>");
fprintf(fd," %s %s",
sig_type,
str_tmp ? str_tmp : "<NULL>");
if(port_value &&port_value[0])
fprintf(fd," = %s", port_value);
fprintf(fd," ;\n");
}
str_tmp = get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"name",0);
fprintf(fd," %s %s ;\n",
strcmp(dir_tmp,"in")? ( strcmp(dir_tmp,"out")? "inout" :"output" ) : "input",
str_tmp ? str_tmp : "<NULL>");
fprintf(fd," %s %s",
sig_type,
str_tmp ? str_tmp : "<NULL>");
if(port_value &&port_value[0])
fprintf(fd," = %s", port_value);
fprintf(fd," ;\n");
}
dbg(1, "verilog_block_netlist(): netlisting %s\n", skip_dir( schematic[currentsch]));
@ -541,8 +543,8 @@ void verilog_netlist(FILE *fd , int verilog_stop)
else print_verilog_element(fd, i) ; /* this is the element line */
}
}
my_free(1084, &type);
}
dbg(1, "verilog_netlist(): end\n");
if(!netlist_count) redraw_hilights(); /*draw_hilight_net(1); */
my_free(1084, &type);
}

96
src/vhdl_netlist.c
View File

@ -270,21 +270,23 @@ void global_vhdl_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<instdef[j].rects[PINLAYER];i++)
{
my_strdup(587, &sig_type,get_tok_value(
instdef[j].boxptr[PINLAYER][i].prop_ptr,"sig_type",0));
my_strdup(588, &port_value, get_tok_value(
instdef[j].boxptr[PINLAYER][i].prop_ptr,"value",2) );
if(!sig_type || sig_type[0]=='\0') my_strdup(589, &sig_type,"std_logic");
my_strdup(590, &dir_tmp, get_tok_value(instdef[j].boxptr[PINLAYER][i].prop_ptr,"dir",0) );
str_tmp = get_tok_value(instdef[j].boxptr[PINLAYER][i].prop_ptr,"name",0);
if(!tmp) fprintf(fd, "port (\n");
if(tmp) fprintf(fd, " ;\n");
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
dir_tmp ? dir_tmp : "<NULL>", sig_type);
my_free(1085, &dir_tmp);
if(port_value &&port_value[0])
fprintf(fd," := %s", port_value);
tmp=1;
if(strcmp(get_tok_value(instdef[j].boxptr[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
my_strdup(587, &sig_type,get_tok_value(
instdef[j].boxptr[PINLAYER][i].prop_ptr,"sig_type",0));
my_strdup(588, &port_value, get_tok_value(
instdef[j].boxptr[PINLAYER][i].prop_ptr,"value",2) );
if(!sig_type || sig_type[0]=='\0') my_strdup(589, &sig_type,"std_logic");
my_strdup(590, &dir_tmp, get_tok_value(instdef[j].boxptr[PINLAYER][i].prop_ptr,"dir",0) );
str_tmp = get_tok_value(instdef[j].boxptr[PINLAYER][i].prop_ptr,"name",0);
if(!tmp) fprintf(fd, "port (\n");
if(tmp) fprintf(fd, " ;\n");
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
dir_tmp ? dir_tmp : "<NULL>", sig_type);
my_free(1085, &dir_tmp);
if(port_value &&port_value[0])
fprintf(fd," := %s", port_value);
tmp=1;
}
}
if(tmp) fprintf(fd, "\n);\n");
fprintf(fd, "end component ;\n\n");
@ -465,21 +467,23 @@ void vhdl_block_netlist(FILE *fd, int i) /*20081204 */
tmp=0;
for(j=0;j<instdef[i].rects[PINLAYER];j++)
{
my_strdup(592, &sig_type,get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"sig_type",0));
my_strdup(593, &port_value, get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"value",2) );
if(!sig_type || sig_type[0]=='\0') my_strdup(594, &sig_type,"std_logic");
my_strdup(595, &dir_tmp, get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"dir",0) );
str_tmp = get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"name",0);
if(tmp) fprintf(fd, " ;\n");
if(!tmp) fprintf(fd,"port (\n");
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
dir_tmp ? dir_tmp : "<NULL>", sig_type);
my_free(1092, &dir_tmp);
if(port_value &&port_value[0])
fprintf(fd," := %s", port_value);
tmp=1;
if(strcmp(get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"vhdl_ignore",0), "true")) {
my_strdup(592, &sig_type,get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"sig_type",0));
my_strdup(593, &port_value, get_tok_value(
instdef[i].boxptr[PINLAYER][j].prop_ptr,"value",2) );
if(!sig_type || sig_type[0]=='\0') my_strdup(594, &sig_type,"std_logic");
my_strdup(595, &dir_tmp, get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"dir",0) );
str_tmp = get_tok_value(instdef[i].boxptr[PINLAYER][j].prop_ptr,"name",0);
if(tmp) fprintf(fd, " ;\n");
if(!tmp) fprintf(fd,"port (\n");
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
dir_tmp ? dir_tmp : "<NULL>", sig_type);
my_free(1092, &dir_tmp);
if(port_value &&port_value[0])
fprintf(fd," := %s", port_value);
tmp=1;
}
}
if(tmp) fprintf(fd, "\n);\n");
@ -541,22 +545,24 @@ void vhdl_block_netlist(FILE *fd, int i) /*20081204 */
tmp=0;
for(k=0;k<instdef[j].rects[PINLAYER];k++)
{
my_strdup(597, &sig_type,get_tok_value(
instdef[j].boxptr[PINLAYER][k].prop_ptr,"sig_type",0));
my_strdup(598, &port_value, get_tok_value(
instdef[j].boxptr[PINLAYER][k].prop_ptr,"value",2) );
if(strcmp(get_tok_value(instdef[j].boxptr[PINLAYER][k].prop_ptr,"vhdl_ignore",0), "true")) {
my_strdup(597, &sig_type,get_tok_value(
instdef[j].boxptr[PINLAYER][k].prop_ptr,"sig_type",0));
my_strdup(598, &port_value, get_tok_value(
instdef[j].boxptr[PINLAYER][k].prop_ptr,"value",2) );
if(!sig_type || sig_type[0]=='\0') my_strdup(599, &sig_type,"std_logic");
my_strdup(600, &dir_tmp, get_tok_value(instdef[j].boxptr[PINLAYER][k].prop_ptr,"dir",0) );
str_tmp = get_tok_value(instdef[j].boxptr[PINLAYER][k].prop_ptr,"name",0);
if(!tmp) fprintf(fd, "port (\n");
if(tmp) fprintf(fd, " ;\n");
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
dir_tmp ? dir_tmp : "<NULL>", sig_type);
my_free(1093, &dir_tmp);
if(port_value &&port_value[0])
fprintf(fd," := %s", port_value);
tmp=1;
if(!sig_type || sig_type[0]=='\0') my_strdup(599, &sig_type,"std_logic");
my_strdup(600, &dir_tmp, get_tok_value(instdef[j].boxptr[PINLAYER][k].prop_ptr,"dir",0) );
str_tmp = get_tok_value(instdef[j].boxptr[PINLAYER][k].prop_ptr,"name",0);
if(!tmp) fprintf(fd, "port (\n");
if(tmp) fprintf(fd, " ;\n");
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
dir_tmp ? dir_tmp : "<NULL>", sig_type);
my_free(1093, &dir_tmp);
if(port_value &&port_value[0])
fprintf(fd," := %s", port_value);
tmp=1;
}
}
if(tmp) fprintf(fd, "\n);\n");
fprintf(fd, "end component ;\n\n");

2
xschem_library/examples/mos_power_ampli.sch
View File

@ -258,5 +258,5 @@ C {spice_probe.sym} 340 -820 0 1 {name=p51 analysis=tran voltage=49.03}
C {spice_probe.sym} 120 -210 0 1 {name=p52 analysis=tran voltage=-42.58}
C {spice_probe.sym} 130 -70 0 1 {name=p53 analysis=tran voltage=-50}
C {opin.sym} 600 -130 0 0 {name=p5 lab=OUT}
C {ipin.sym} 530 -180 0 0 {name=p1 lab=MINUS}
C {ipin.sym} 530 -180 0 0 {name=p1 lab=MINUS spice_ignore=true verilog_ignore=true vhdl_ignore=true}
C {ipin.sym} 530 -140 0 0 {name=p4 lab=VSS}

32
xschem_library/examples/mos_power_ampli.sym
View File

@ -1,32 +1,30 @@
v {xschem version=2.9.5 file_version=1.1}
v {xschem version=2.9.7 file_version=1.1}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
T {@symname} -85.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -62 0 0 0.2 0.2 {}
L 4 -130 -50 130 -50 {}
L 4 -130 50 130 50 {}
L 4 -130 -50 -130 50 {}
L 4 130 -50 130 50 {}
B 5 -152.5 -42.5 -147.5 -37.5 {name=MINUS dir=in name=p1 spice_ignore=true verilog_ignore=true vhdl_ignore=true}
L 4 -150 -40 -130 -40 {}
L 4 -150 -20 -130 -20 {}
L 4 -150 0 -130 0 {}
L 4 130 -40 150 -40 {}
L 4 -150 20 -130 20 {}
L 4 -150 40 -130 40 {}
B 5 -152.5 -42.5 -147.5 -37.5 {name=MINUS dir=in }
B 5 -152.5 -22.5 -147.5 -17.5 {name=PLUS dir=in }
B 5 -152.5 -2.5 -147.5 2.5 {name=VSS dir=in }
B 5 147.5 -42.5 152.5 -37.5 {name=OUT dir=out }
B 5 -152.5 17.5 -147.5 22.5 {name=VPP dir=in }
B 5 -152.5 37.5 -147.5 42.5 {name=VNN dir=in }
T {@symname} -67.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -62 0 0 0.2 0.2 {}
T {MINUS} -125 -44 0 0 0.2 0.2 {}
B 5 -152.5 -22.5 -147.5 -17.5 {name=PLUS dir=in name=p0 }
L 4 -150 -20 -130 -20 {}
T {PLUS} -125 -24 0 0 0.2 0.2 {}
B 5 -152.5 -2.5 -147.5 2.5 {name=VSS dir=in name=p4 }
L 4 -150 0 -130 0 {}
T {VSS} -125 -4 0 0 0.2 0.2 {}
B 5 147.5 -42.5 152.5 -37.5 {name=OUT dir=out name=p5 }
L 4 130 -40 150 -40 {}
T {OUT} 125 -44 0 1 0.2 0.2 {}
B 5 -152.5 17.5 -147.5 22.5 {name=VPP dir=in name=p2 }
L 4 -150 20 -130 20 {}
T {VPP} -125 16 0 0 0.2 0.2 {}
B 5 -152.5 37.5 -147.5 42.5 {name=VNN dir=in name=p3 }
L 4 -150 40 -130 40 {}
T {VNN} -125 36 0 0 0.2 0.2 {}