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module parameter declaration follow verilog2001 format if enabled ( #( parameter aaa=1, bbb=2, .... ) list before port list)

This commit is contained in:
Stefan Frederik 2022-04-25 11:23:28 +02:00
parent 89f538ffa1
commit 9b46db7341
1 changed files with 10 additions and 6 deletions
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16
src/convert_to_verilog2001.awk
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@ -27,7 +27,9 @@ NF==3 && $0 ~/^module/ {
module=1
port_decl=0
parameter = ""
ports = ""
comma=0
sub(/[ \t]*\(/, "")
print
next
}
@ -43,21 +45,23 @@ port_decl==1 && $1 ~ /^(output|input|inout)$/{
getline
sub(/;[ \t]*$/,"")
$1 = dir " " $1
if(comma) printf ",\n"
printf " %s", $0
if(comma) ports = ports ",\n"
ports = ports " " $0
comma=1
next
}
port_decl==1 && $0 ~ /^parameter/{
if(parameter!="") parameter = parameter "\n"
parameter = parameter $0
sub(/[ \t]*;[ \t]*$/, "")
if(parameter!="") parameter = parameter ",\n"
parameter = parameter " " $0
next
}
port_decl==1 && $0 ~/^[ \t]*$/{
port_decl=0
printf "\n);\n"
print parameter
if(parameter) print "#(\n" parameter "\n)"
print "(\n" ports "\n);"
next
}