Allow wave expressions with spaces on a single line without quotes ("...."). Quotes can be used for wave expression on multiple lines. Side effect: multiple nodes can no more be specified on a single line separated with spaces. Use newlines
This commit is contained in:
parent
75b5cc13f4
commit
963e877497
12
src/draw.c
12
src/draw.c
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@ -2424,7 +2424,7 @@ int graph_fullyzoom(xRect *r, Graph_ctx *gr, int graph_dataset)
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start = (gr->gx1 <= gr->gx2) ? gr->gx1 : gr->gx2;
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start = (gr->gx1 <= gr->gx2) ? gr->gx1 : gr->gx2;
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end = (gr->gx1 <= gr->gx2) ? gr->gx2 : gr->gx1;
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end = (gr->gx1 <= gr->gx2) ? gr->gx2 : gr->gx1;
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while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 4, &saven)) ) {
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while( (ntok = my_strtok_r(nptr, "\n", "\"", 4, &saven)) ) {
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int allow_wrap = 1;
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int allow_wrap = 1;
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char *nd = NULL;
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char *nd = NULL;
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char str_extra_idx[30];
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char str_extra_idx[30];
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@ -3292,9 +3292,9 @@ int edit_wave_attributes(int what, int i, Graph_ctx *gr)
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nptr = node;
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nptr = node;
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cptr = color;
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cptr = color;
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sptr = sweep;
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sptr = sweep;
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n_nodes = count_items(node, " \t\n", "\"");
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n_nodes = count_items(node, "\n", "\"");
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/* process each node given in "node" attribute, get also associated color/sweep var if any */
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/* process each node given in "node" attribute, get also associated color/sweep var if any */
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while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 0, &saven)) ) {
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while( (ntok = my_strtok_r(nptr, "\n", "\"", 0, &saven)) ) {
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ctok = my_strtok_r(cptr, " ", "", 0, &savec);
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ctok = my_strtok_r(cptr, " ", "", 0, &savec);
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stok = my_strtok_r(sptr, "\t\n ", "\"", 0, &saves);
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stok = my_strtok_r(sptr, "\t\n ", "\"", 0, &saves);
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nptr = cptr = sptr = NULL;
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nptr = cptr = sptr = NULL;
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@ -3484,7 +3484,7 @@ int find_closest_wave(int i, Graph_ctx *gr)
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nptr = node;
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nptr = node;
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sptr = sweep;
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sptr = sweep;
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/* process each node given in "node" attribute, get also associated sweep var if any*/
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/* process each node given in "node" attribute, get also associated sweep var if any*/
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while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 0, &saven)) ) {
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while( (ntok = my_strtok_r(nptr, "\n", "\"", 0, &saven)) ) {
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if(strstr(ntok, ",")) {
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if(strstr(ntok, ",")) {
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if(find_nth(ntok, ";,", "\"", 0, 2)[0]) continue; /* bus signal: skip */
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if(find_nth(ntok, ";,", "\"", 0, 2)[0]) continue; /* bus signal: skip */
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}
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}
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@ -3700,10 +3700,10 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
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nptr = node;
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nptr = node;
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cptr = color;
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cptr = color;
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sptr = sweep;
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sptr = sweep;
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n_nodes = count_items(node, "\n\t ", "\"");
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n_nodes = count_items(node, "\n", "\"");
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/* process each node given in "node" attribute, get also associated color/sweep var if any*/
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/* process each node given in "node" attribute, get also associated color/sweep var if any*/
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while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 4, &saven)) ) {
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while( (ntok = my_strtok_r(nptr, "\n", "\"", 4, &saven)) ) {
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int valid_rawfile = 1;
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int valid_rawfile = 1;
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int allow_wrap = 1;
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int allow_wrap = 1;
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char *nd = NULL;
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char *nd = NULL;
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@ -136,15 +136,37 @@ char *my_fgets(FILE *fd, size_t *line_len)
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}
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}
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/* split a string into tokens like standard strtok_r,
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/* split a string into tokens like standard strtok_r,
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* if quote string is not empty any character matching quote is considered a quoting
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* if keep_quote == 0:
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* character, removed from input and all characters before next quote are considered
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* if quote string is not empty any character matching quote is considered a quoting
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* as part of the token. backslash can be used to enter literal quoting characters and
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* character, removed from input and all characters before next quote are considered
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* literal backslashes.
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* as part of the token. backslash can be used to enter literal quoting characters and
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* behavior described above can be changed if keep_quote is not zero:
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* literal backslashes. Escaping backslash is removed from tokens.
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* keep_quote == 1: keep quotes and backslahes
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* if keep_quote == 1:
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* keep_quote == 4: remove surrounding "...", keep everything in between
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* keep quotes and backslahes
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* if quote is empty no backslash is removed from input and behavior is identical
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* if keep_quote == 4:
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* remove quoting characters, keep backslashes
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* if quote is empty no backslash/quote is removed from input and behavior is identical
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* to strtok_r
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* to strtok_r
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*
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* Example:
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* my_strtok_r("aaa \\\"bbb\\\" \"ccc ddd\" eee", " ", "\"", 0);
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* aaa
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* "bbb"
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* ccc ddd
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* eee
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*
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* my_strtok_r("aaa \\\"bbb\\\" \"ccc ddd\" eee", " ", "\"", 1);
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* aaa
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* \"bbb\"
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* "ccc ddd"
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* eee
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*
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* my_strtok_r("aaa \\\"bbb\\\" \"ccc ddd\" eee", " ", "\"", 4);
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* aaa
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* \"bbb\"
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* ccc ddd
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* eee
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*
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*/
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*/
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char *my_strtok_r(char *str, const char *delim, const char *quote, int keep_quote, char **saveptr)
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char *my_strtok_r(char *str, const char *delim, const char *quote, int keep_quote, char **saveptr)
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{
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{
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@ -163,11 +185,11 @@ char *my_strtok_r(char *str, const char *delim, const char *quote, int keep_quot
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if(ne) *(*saveptr - ne) = **saveptr; /* shift back eating escapes / quotes */
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if(ne) *(*saveptr - ne) = **saveptr; /* shift back eating escapes / quotes */
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if(!e && strchr(quote, **saveptr)) {
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if(!e && strchr(quote, **saveptr)) {
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q = !q;
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q = !q;
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if(keep_quote != 1) ++ne;
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if(!(keep_quote & 1)) ++ne; /* remove quoting character */
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}
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}
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if(!e && **saveptr == '\\') { /* do not skip backslashes either */
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if(quote[0] && !e && **saveptr == '\\') { /* do not skip backslashes either */
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e = 1;
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e = 1;
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if(keep_quote == 0) ++ne;
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if(!(keep_quote & 5)) ++ne; /* remove escaping backslash */
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} else e = 0;
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} else e = 0;
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++(*saveptr);
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++(*saveptr);
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}
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}
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@ -2268,7 +2268,7 @@ proc graph_edit_wave {n n_wave} {
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set graph_selected $n
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set graph_selected $n
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set graph_sel_wave $n_wave
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set graph_sel_wave $n_wave
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set col [xschem getprop rect 2 $graph_selected color]
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set col [xschem getprop rect 2 $graph_selected color]
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set node [xschem getprop rect 2 $graph_selected node]
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set node [xschem my_strtok_r [xschem getprop rect 2 $graph_selected node] \n \" 0]
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# add default colors if unspecified in col
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# add default colors if unspecified in col
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set i 0
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set i 0
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foreach graph_node $node {
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foreach graph_node $node {
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@ -2536,16 +2536,22 @@ proc graph_tag_nodes {txt} {
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set col [xschem getprop rect 2 $graph_selected color]
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set col [xschem getprop rect 2 $graph_selected color]
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set col [string trim $col " \n"]
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set col [string trim $col " \n"]
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}
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}
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# non capturing `tcleval(` at beginning and `)` at end
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set regx {(?:tcleval\(\n*)?("[^"]+"|[^ \t\n)]+)(?:\))?}
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set start 0
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if {[regexp {^tcleval\(} $txt]} {
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set start 8
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regsub {\)[ \n]*$} $txt {} txt
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}
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set regx {("[^"]+")|([^\n]+)}
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set tt {}
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set tt {}
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set cc {}
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set cc {}
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set start 0
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while {[regexp -indices -start $start $regx $txt idxall]} {
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lappend tt [lindex $idxall 0]
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while {[regexp -indices -start $start $regx $txt idxall idx]} {
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set ccc [lindex $idxall 1]
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lappend tt [lindex $idx 0]
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lappend cc $ccc
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set start [expr {[lindex $idx 1] + 1}]
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set start [expr {$ccc + 1}]
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lappend cc $start
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}
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}
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if { [winfo exists .graphdialog.center.right.text1] } {
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if { [winfo exists .graphdialog.center.right.text1] } {
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set n 0
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set n 0
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@ -2558,7 +2564,7 @@ proc graph_tag_nodes {txt} {
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lappend col $graph_sel_color
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lappend col $graph_sel_color
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}
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}
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set b [lindex $tctx::colors $col_idx]
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set b [lindex $tctx::colors $col_idx]
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.graphdialog.center.right.text1 tag add t$n "1.0 + $t chars" "1.0 + $c chars"
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.graphdialog.center.right.text1 tag add t$n "1.0 + $t chars" "1.1 + $c chars"
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if { [info tclversion] > 8.4} {
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if { [info tclversion] > 8.4} {
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.graphdialog.center.right.text1 tag configure t$n -background $b -selectbackground grey40
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.graphdialog.center.right.text1 tag configure t$n -background $b -selectbackground grey40
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} else {
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} else {
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -60,11 +60,11 @@ L 4 2.5 -22.5 7.5 -22.5 {}
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L 4 5 -25 5 -20 {}
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L 4 5 -25 5 -20 {}
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B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1 goto=1}
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B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1 goto=1}
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B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2 goto=0}
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B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2 goto=0}
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T {@name} -15 -13.75 0 1 0.2 0.2 {}
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T {@value} 15 -3.75 0 0 0.2 0.2 {}
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T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
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T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
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T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15 hide=instance}
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T {m=@m} -15 1.25 0 1 0.2 0.2 {}
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T {@name} 15 -18.75 0 0 0.2 0.2 {}
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T {@spice_get_current} 12.5 -16.25 0 0 0.2 0.2 {layer=17}
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T {@value} 15 -6.25 0 0 0.2 0.2 {}
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T {m=@m} 15 6.25 0 0 0.2 0.2 {}
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T {@spice_get_current} -10 5 0 1 0.2 0.2 {layer=17}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.6RC file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -49,8 +49,9 @@ divy = 6
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x1=2.7755576e-17
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x1=2.7755576e-17
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x2=3
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x2=3
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divx=6
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divx=6
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node="a z"
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node="a
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color="7 6"
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z"
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color="7 4"
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sweep="z a"
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sweep="z a"
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sim_type=dc
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sim_type=dc
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@ -1,4 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -84,8 +84,8 @@ dataset=0
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unitx=m
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unitx=m
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color="8 7"
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color="8 7"
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node="tcleval(\\"Xm2 Power;$\{path\}outi vnn - i(v.$\{path\}vd) *\\"
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node="tcleval(Xm2 Power;$\{path\}outi vnn - i(v.$\{path\}vd) *
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\\"Average;$\{path\}outi vnn - i(v.$\{path\}vd) * 200u ravg()\\")"
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Average;$\{path\}outi vnn - i(v.$\{path\}vd) * 200u ravg())"
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jpeg_quality=30
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jpeg_quality=30
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xlabmag=1.4}
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xlabmag=1.4}
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B 2 960 -1050 1094 -987 {flags=image
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B 2 960 -1050 1094 -987 {flags=image
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@ -1,4 +1,4 @@
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v {xschem version=3.4.6RC file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -81,9 +81,9 @@ divx=10
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unitx=m
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unitx=m
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color="4 7"
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color="19 7"
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node="\\"supply power;i(vcurrvnn) vnn * i(vcurrvpp) vpp * +\\"
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node="supply power;i(vcurrvnn) vnn * i(vcurrvpp) vpp * +
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\\"running average supply power;i(vcurrvnn) vnn * i(vcurrvpp) vpp * + 200u ravg()\\""
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running average supply power;i(vcurrvnn) vnn * i(vcurrvpp) vpp * + 200u ravg()"
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linewidth_mult=2.3
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linewidth_mult=2.3
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autoload=0
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autoload=0
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@ -1,4 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -83,11 +83,11 @@ divx=5
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subdivx=4
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subdivx=4
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node="en%0
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node="en%0
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cal%0
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cal%0
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\\"SAOUT#3; vss,saout%3\\"
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SAOUT#3; vss,saout%3
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--slow--
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--slow--
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\\"SAOUT#15; vss,saout%15\\"
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SAOUT#15; vss,saout%15
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--failure--
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--failure--
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\\"SAOUT#70; vss,saout%70\\""
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SAOUT#70; vss,saout%70"
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color="4 4 4 8 8 7 7"
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color="4 4 4 8 8 7 7"
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dataset=-1
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dataset=-1
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digital=1
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digital=1
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@ -109,8 +109,8 @@ unitx=n
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dataset=-1
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dataset=-1
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color="4 7"
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color="4 7"
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node="\\"power dset 97 ; i(vvcc) vcc * % 23\\"
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node="power dset 97 ; i(vvcc) vcc * % 23
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\\"power dset 70 ; i(vvcc) vcc * % 70\\""
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power dset 70 ; i(vvcc) vcc * % 70"
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subdivy=4
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subdivy=4
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linewidth_mult=1.0}
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linewidth_mult=1.0}
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T {CAL} 140 -180 0 1 0.4 0.4 {}
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T {CAL} 140 -180 0 1 0.4 0.4 {}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.6RC file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -131,11 +131,12 @@ x2=0.0010293582
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divx=9
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divx=9
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unitx=m subdivx=4
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unitx=m subdivx=4
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color="7 4 6 10"
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color="7 4 6 8 4"
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node="\\"Panel power; i(Vpanel) v(PANEL) *\\"
|
node="Panel power; i(Vpanel)\\\\
|
||||||
\\"Led power; i(Vled) v(LED) *\\"
|
v(PANEL) *
|
||||||
\\"Avg.Pan. Pwr; i(Vpanel) v(PANEL) * 20u ravg()\\"
|
Led power; i(Vled) v(LED) *
|
||||||
\\"SUN \\\\%; SUN 100 *\\""
|
Avg.Pan. Pwr; i(Vpanel) v(PANEL) * 20u ravg()
|
||||||
|
SUN \\\\%; SUN 100 *"
|
||||||
hilight_wave=-1
|
hilight_wave=-1
|
||||||
jpeg_quality=30
|
jpeg_quality=30
|
||||||
linewidth_mult=2.0
|
linewidth_mult=2.0
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue