Allow wave expressions with spaces on a single line without quotes ("...."). Quotes can be used for wave expression on multiple lines. Side effect: multiple nodes can no more be specified on a single line separated with spaces. Use newlines

This commit is contained in:
stefan schippers 2024-12-05 02:54:08 +01:00
parent 75b5cc13f4
commit 963e877497
9 changed files with 84 additions and 54 deletions

View File

@ -2424,7 +2424,7 @@ int graph_fullyzoom(xRect *r, Graph_ctx *gr, int graph_dataset)
start = (gr->gx1 <= gr->gx2) ? gr->gx1 : gr->gx2; start = (gr->gx1 <= gr->gx2) ? gr->gx1 : gr->gx2;
end = (gr->gx1 <= gr->gx2) ? gr->gx2 : gr->gx1; end = (gr->gx1 <= gr->gx2) ? gr->gx2 : gr->gx1;
while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 4, &saven)) ) { while( (ntok = my_strtok_r(nptr, "\n", "\"", 4, &saven)) ) {
int allow_wrap = 1; int allow_wrap = 1;
char *nd = NULL; char *nd = NULL;
char str_extra_idx[30]; char str_extra_idx[30];
@ -3292,9 +3292,9 @@ int edit_wave_attributes(int what, int i, Graph_ctx *gr)
nptr = node; nptr = node;
cptr = color; cptr = color;
sptr = sweep; sptr = sweep;
n_nodes = count_items(node, " \t\n", "\""); n_nodes = count_items(node, "\n", "\"");
/* process each node given in "node" attribute, get also associated color/sweep var if any */ /* process each node given in "node" attribute, get also associated color/sweep var if any */
while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 0, &saven)) ) { while( (ntok = my_strtok_r(nptr, "\n", "\"", 0, &saven)) ) {
ctok = my_strtok_r(cptr, " ", "", 0, &savec); ctok = my_strtok_r(cptr, " ", "", 0, &savec);
stok = my_strtok_r(sptr, "\t\n ", "\"", 0, &saves); stok = my_strtok_r(sptr, "\t\n ", "\"", 0, &saves);
nptr = cptr = sptr = NULL; nptr = cptr = sptr = NULL;
@ -3484,7 +3484,7 @@ int find_closest_wave(int i, Graph_ctx *gr)
nptr = node; nptr = node;
sptr = sweep; sptr = sweep;
/* process each node given in "node" attribute, get also associated sweep var if any*/ /* process each node given in "node" attribute, get also associated sweep var if any*/
while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 0, &saven)) ) { while( (ntok = my_strtok_r(nptr, "\n", "\"", 0, &saven)) ) {
if(strstr(ntok, ",")) { if(strstr(ntok, ",")) {
if(find_nth(ntok, ";,", "\"", 0, 2)[0]) continue; /* bus signal: skip */ if(find_nth(ntok, ";,", "\"", 0, 2)[0]) continue; /* bus signal: skip */
} }
@ -3700,10 +3700,10 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
nptr = node; nptr = node;
cptr = color; cptr = color;
sptr = sweep; sptr = sweep;
n_nodes = count_items(node, "\n\t ", "\""); n_nodes = count_items(node, "\n", "\"");
/* process each node given in "node" attribute, get also associated color/sweep var if any*/ /* process each node given in "node" attribute, get also associated color/sweep var if any*/
while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 4, &saven)) ) { while( (ntok = my_strtok_r(nptr, "\n", "\"", 4, &saven)) ) {
int valid_rawfile = 1; int valid_rawfile = 1;
int allow_wrap = 1; int allow_wrap = 1;
char *nd = NULL; char *nd = NULL;

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@ -136,15 +136,37 @@ char *my_fgets(FILE *fd, size_t *line_len)
} }
/* split a string into tokens like standard strtok_r, /* split a string into tokens like standard strtok_r,
* if keep_quote == 0:
* if quote string is not empty any character matching quote is considered a quoting * if quote string is not empty any character matching quote is considered a quoting
* character, removed from input and all characters before next quote are considered * character, removed from input and all characters before next quote are considered
* as part of the token. backslash can be used to enter literal quoting characters and * as part of the token. backslash can be used to enter literal quoting characters and
* literal backslashes. * literal backslashes. Escaping backslash is removed from tokens.
* behavior described above can be changed if keep_quote is not zero: * if keep_quote == 1:
* keep_quote == 1: keep quotes and backslahes * keep quotes and backslahes
* keep_quote == 4: remove surrounding "...", keep everything in between * if keep_quote == 4:
* if quote is empty no backslash is removed from input and behavior is identical * remove quoting characters, keep backslashes
* if quote is empty no backslash/quote is removed from input and behavior is identical
* to strtok_r * to strtok_r
*
* Example:
* my_strtok_r("aaa \\\"bbb\\\" \"ccc ddd\" eee", " ", "\"", 0);
* aaa
* "bbb"
* ccc ddd
* eee
*
* my_strtok_r("aaa \\\"bbb\\\" \"ccc ddd\" eee", " ", "\"", 1);
* aaa
* \"bbb\"
* "ccc ddd"
* eee
*
* my_strtok_r("aaa \\\"bbb\\\" \"ccc ddd\" eee", " ", "\"", 4);
* aaa
* \"bbb\"
* ccc ddd
* eee
*
*/ */
char *my_strtok_r(char *str, const char *delim, const char *quote, int keep_quote, char **saveptr) char *my_strtok_r(char *str, const char *delim, const char *quote, int keep_quote, char **saveptr)
{ {
@ -163,11 +185,11 @@ char *my_strtok_r(char *str, const char *delim, const char *quote, int keep_quot
if(ne) *(*saveptr - ne) = **saveptr; /* shift back eating escapes / quotes */ if(ne) *(*saveptr - ne) = **saveptr; /* shift back eating escapes / quotes */
if(!e && strchr(quote, **saveptr)) { if(!e && strchr(quote, **saveptr)) {
q = !q; q = !q;
if(keep_quote != 1) ++ne; if(!(keep_quote & 1)) ++ne; /* remove quoting character */
} }
if(!e && **saveptr == '\\') { /* do not skip backslashes either */ if(quote[0] && !e && **saveptr == '\\') { /* do not skip backslashes either */
e = 1; e = 1;
if(keep_quote == 0) ++ne; if(!(keep_quote & 5)) ++ne; /* remove escaping backslash */
} else e = 0; } else e = 0;
++(*saveptr); ++(*saveptr);
} }

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@ -2268,7 +2268,7 @@ proc graph_edit_wave {n n_wave} {
set graph_selected $n set graph_selected $n
set graph_sel_wave $n_wave set graph_sel_wave $n_wave
set col [xschem getprop rect 2 $graph_selected color] set col [xschem getprop rect 2 $graph_selected color]
set node [xschem getprop rect 2 $graph_selected node] set node [xschem my_strtok_r [xschem getprop rect 2 $graph_selected node] \n \" 0]
# add default colors if unspecified in col # add default colors if unspecified in col
set i 0 set i 0
foreach graph_node $node { foreach graph_node $node {
@ -2536,16 +2536,22 @@ proc graph_tag_nodes {txt} {
set col [xschem getprop rect 2 $graph_selected color] set col [xschem getprop rect 2 $graph_selected color]
set col [string trim $col " \n"] set col [string trim $col " \n"]
} }
# non capturing `tcleval(` at beginning and `)` at end
set regx {(?:tcleval\(\n*)?("[^"]+"|[^ \t\n)]+)(?:\))?}
set start 0
if {[regexp {^tcleval\(} $txt]} {
set start 8
regsub {\)[ \n]*$} $txt {} txt
}
set regx {("[^"]+")|([^\n]+)}
set tt {} set tt {}
set cc {} set cc {}
set start 0 while {[regexp -indices -start $start $regx $txt idxall]} {
lappend tt [lindex $idxall 0]
while {[regexp -indices -start $start $regx $txt idxall idx]} { set ccc [lindex $idxall 1]
lappend tt [lindex $idx 0] lappend cc $ccc
set start [expr {[lindex $idx 1] + 1}] set start [expr {$ccc + 1}]
lappend cc $start
} }
if { [winfo exists .graphdialog.center.right.text1] } { if { [winfo exists .graphdialog.center.right.text1] } {
set n 0 set n 0
@ -2558,7 +2564,7 @@ proc graph_tag_nodes {txt} {
lappend col $graph_sel_color lappend col $graph_sel_color
} }
set b [lindex $tctx::colors $col_idx] set b [lindex $tctx::colors $col_idx]
.graphdialog.center.right.text1 tag add t$n "1.0 + $t chars" "1.0 + $c chars" .graphdialog.center.right.text1 tag add t$n "1.0 + $t chars" "1.1 + $c chars"
if { [info tclversion] > 8.4} { if { [info tclversion] > 8.4} {
.graphdialog.center.right.text1 tag configure t$n -background $b -selectbackground grey40 .graphdialog.center.right.text1 tag configure t$n -background $b -selectbackground grey40
} else { } else {

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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2 v {xschem version=3.4.6 file_version=1.2
* *
* This file is part of XSCHEM, * This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -60,11 +60,11 @@ L 4 2.5 -22.5 7.5 -22.5 {}
L 4 5 -25 5 -20 {} L 4 5 -25 5 -20 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1 goto=1} B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1 goto=1}
B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2 goto=0} B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2 goto=0}
T {@name} -15 -13.75 0 1 0.2 0.2 {}
T {@value} 15 -3.75 0 0 0.2 0.2 {}
T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13} T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13} T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15 hide=instance} T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15 hide=instance}
T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15 hide=instance} T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15 hide=instance}
T {m=@m} -15 1.25 0 1 0.2 0.2 {} T {@name} 15 -18.75 0 0 0.2 0.2 {}
T {@spice_get_current} 12.5 -16.25 0 0 0.2 0.2 {layer=17} T {@value} 15 -6.25 0 0 0.2 0.2 {}
T {m=@m} 15 6.25 0 0 0.2 0.2 {}
T {@spice_get_current} -10 5 0 1 0.2 0.2 {layer=17}

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@ -1,4 +1,4 @@
v {xschem version=3.4.6RC file_version=1.2 v {xschem version=3.4.6 file_version=1.2
* *
* This file is part of XSCHEM, * This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -49,8 +49,9 @@ divy = 6
x1=2.7755576e-17 x1=2.7755576e-17
x2=3 x2=3
divx=6 divx=6
node="a z" node="a
color="7 6" z"
color="7 4"
sweep="z a" sweep="z a"
sim_type=dc sim_type=dc

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@ -1,4 +1,4 @@
v {xschem version=3.4.5 file_version=1.2 v {xschem version=3.4.6 file_version=1.2
* *
* This file is part of XSCHEM, * This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -84,8 +84,8 @@ dataset=0
unitx=m unitx=m
color="8 7" color="8 7"
node="tcleval(\\"Xm2 Power;$\{path\}outi vnn - i(v.$\{path\}vd) *\\" node="tcleval(Xm2 Power;$\{path\}outi vnn - i(v.$\{path\}vd) *
\\"Average;$\{path\}outi vnn - i(v.$\{path\}vd) * 200u ravg()\\")" Average;$\{path\}outi vnn - i(v.$\{path\}vd) * 200u ravg())"
jpeg_quality=30 jpeg_quality=30
xlabmag=1.4} xlabmag=1.4}
B 2 960 -1050 1094 -987 {flags=image B 2 960 -1050 1094 -987 {flags=image

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@ -1,4 +1,4 @@
v {xschem version=3.4.6RC file_version=1.2 v {xschem version=3.4.6 file_version=1.2
* *
* This file is part of XSCHEM, * This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -81,9 +81,9 @@ divx=10
unitx=m unitx=m
color="4 7" color="19 7"
node="\\"supply power;i(vcurrvnn) vnn * i(vcurrvpp) vpp * +\\" node="supply power;i(vcurrvnn) vnn * i(vcurrvpp) vpp * +
\\"running average supply power;i(vcurrvnn) vnn * i(vcurrvpp) vpp * + 200u ravg()\\"" running average supply power;i(vcurrvnn) vnn * i(vcurrvpp) vpp * + 200u ravg()"
linewidth_mult=2.3 linewidth_mult=2.3
autoload=0 autoload=0

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@ -1,4 +1,4 @@
v {xschem version=3.4.5 file_version=1.2 v {xschem version=3.4.6 file_version=1.2
* *
* This file is part of XSCHEM, * This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -83,11 +83,11 @@ divx=5
subdivx=4 subdivx=4
node="en%0 node="en%0
cal%0 cal%0
\\"SAOUT#3; vss,saout%3\\" SAOUT#3; vss,saout%3
--slow-- --slow--
\\"SAOUT#15; vss,saout%15\\" SAOUT#15; vss,saout%15
--failure-- --failure--
\\"SAOUT#70; vss,saout%70\\"" SAOUT#70; vss,saout%70"
color="4 4 4 8 8 7 7" color="4 4 4 8 8 7 7"
dataset=-1 dataset=-1
digital=1 digital=1
@ -109,8 +109,8 @@ unitx=n
dataset=-1 dataset=-1
color="4 7" color="4 7"
node="\\"power dset 97 ; i(vvcc) vcc * % 23\\" node="power dset 97 ; i(vvcc) vcc * % 23
\\"power dset 70 ; i(vvcc) vcc * % 70\\"" power dset 70 ; i(vvcc) vcc * % 70"
subdivy=4 subdivy=4
linewidth_mult=1.0} linewidth_mult=1.0}
T {CAL} 140 -180 0 1 0.4 0.4 {} T {CAL} 140 -180 0 1 0.4 0.4 {}

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@ -1,4 +1,4 @@
v {xschem version=3.4.6RC file_version=1.2 v {xschem version=3.4.6 file_version=1.2
* *
* This file is part of XSCHEM, * This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -131,11 +131,12 @@ x2=0.0010293582
divx=9 divx=9
unitx=m subdivx=4 unitx=m subdivx=4
color="7 4 6 10" color="7 4 6 8 4"
node="\\"Panel power; i(Vpanel) v(PANEL) *\\" node="Panel power; i(Vpanel)\\\\
\\"Led power; i(Vled) v(LED) *\\" v(PANEL) *
\\"Avg.Pan. Pwr; i(Vpanel) v(PANEL) * 20u ravg()\\" Led power; i(Vled) v(LED) *
\\"SUN \\\\%; SUN 100 *\\"" Avg.Pan. Pwr; i(Vpanel) v(PANEL) * 20u ravg()
SUN \\\\%; SUN 100 *"
hilight_wave=-1 hilight_wave=-1
jpeg_quality=30 jpeg_quality=30
linewidth_mult=2.0 linewidth_mult=2.0