added xschemrc tcl var "auto_set_wire_bus": if set to 1 (default: 0) wires with/without bus labels (xxx[3:0]) will get bus=1 attribute set/deleted automatically.

This commit is contained in:
stefan schippers 2026-04-30 14:56:55 +02:00
parent 8006c0cfbb
commit 8c844cc0c9
6 changed files with 63 additions and 1 deletions

View File

@ -5447,6 +5447,10 @@ void draw(void)
++i;
if(i >= xctx->wires) break;
}
if(tclgetboolvar("auto_set_wire_bus")) auto_set_wire_bus(i, i + 1);
if(xctx->wire[i].bus == -1.0) {
if(skip_wire(i))
drawline(GRIDLAYER, THICK, xctx->wire[i].x1,xctx->wire[i].y1,

View File

@ -1609,6 +1609,54 @@ void show_unconnected_pins(void)
unselect_all(1);
}
void auto_set_wire_bus(int start, int end)
{
int i, bus = 0;
double oldbus;
regex_t re;
int cc;
if(xctx->netlist_count) return; /* do this only in top level */
if(end > xctx->wires) return;
if(start < 0) return;
cc = WIRELAYER; if(xctx->only_probes) cc = GRIDLAYER;
regcomp(&re, "(.+\\[.+(:|\\.\\.)[^.]+\\])|(,)", REG_NOSUB | REG_EXTENDED);
for(i = start;i < end; ++i) {
bus = 0;
oldbus = xctx->wire[i].bus;
if(!regexec(&re, xctx->wire[i].node, 0 , NULL, 0) ) bus = 1;
if( (oldbus == 0.0 && bus == 1) || (oldbus == -1.0 && bus == 0) ) {
dbg(1, "auto_set_wire_bus(): i=%d, oldbus=%g bus=%d\n", i, oldbus, bus);
set_modify(1);
dbg(1, "auto_set_wire_bus(): wire[%d].prop_ptr=%s\n", i, xctx->wire[i].prop_ptr);
my_strdup(_ALLOC_ID_, &xctx->wire[i].prop_ptr,
subst_token(xctx->wire[i].prop_ptr, "bus", bus ? "1" : NULL));
xctx->wire[i].bus = bus ? -1.0 : 0.0;
dbg(1, "auto_set_wire_bus(): wire[%d].bus=%g, lab=%s\n", i, xctx->wire[i].bus, xctx->wire[i].node);
dbg(1, "auto_set_wire_bus(): wire[%d].prop_ptr=%s\n", i, xctx->wire[i].prop_ptr);
if(xctx->wire[i].bus == -1.0) {
if(skip_wire(i))
drawline(GRIDLAYER, THICK, xctx->wire[i].x1,xctx->wire[i].y1,
xctx->wire[i].x2,xctx->wire[i].y2, xctx->wire[i].bus, 2, NULL);
else
drawline(cc, THICK, xctx->wire[i].x1,xctx->wire[i].y1,
xctx->wire[i].x2,xctx->wire[i].y2, xctx->wire[i].bus, 0, NULL);
}
else if(skip_wire(i))
drawline(GRIDLAYER, NOW, xctx->wire[i].x1,xctx->wire[i].y1,
xctx->wire[i].x2,xctx->wire[i].y2, xctx->wire[i].bus, 2, NULL);
else
drawline(cc, ADD, xctx->wire[i].x1,xctx->wire[i].y1,
xctx->wire[i].x2,xctx->wire[i].y2, xctx->wire[i].bus, 0, NULL);
}
}
regfree(&re);
}
int prepare_netlist_structs(int for_netl)
{
int err = 0;

View File

@ -6373,6 +6373,9 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
xctx->prep_hash_wires=0;
hash_wires();
}
else if(argc > 2 && atoi(argv[2]) == 7) {
auto_set_wire_bus(0, xctx->wires);
}
else if(argc > 5 && atoi(argv[2]) == 2) {
/* example: xschem test 2 .xctrl. LDCP_REF 8 */
prepare_netlist_structs(0);

View File

@ -1774,6 +1774,7 @@ extern void display_hilights(int what, char **str);
extern void redraw_hilights(int clear);
extern void set_tcl_netlist_type(void);
extern void show_unconnected_pins(void);
extern void auto_set_wire_bus(int start, int end);
extern int prepare_netlist_structs(int for_netlist);
extern int skip_wire(int i);
extern int skip_instance(int i, int skip_short, int lvs_ignore);

View File

@ -9711,7 +9711,8 @@ proc no_open_dialogs {} {
set tctx::global_list {
INITIALINSTDIR INITIALLOADDIR INITIALPROPDIR INITIALTEXTDIR PDK PDK_ROOT SKYWATER_MODELS
SKYWATER_STDCELLS XSCHEM_LIBRARY_PATH add_all_windows_drives auto_hilight
auto_hilight_graph_nodes autofocus_mainwindow autotrim_wires bespice_listen_port big_grid_points
auto_hilight_graph_nodes autofocus_mainwindow auto_set_wire_bus autotrim_wires
bespice_listen_port big_grid_points
bus_replacement_char cadence_compat cadgrid cadlayers cadsnap cairo_font_name cairo_font_scale
change_lw color_ps compare_sch constr_mv copy_cell crosshair_layer crosshair_size cursor_2_hook
custom_label_prefix custom_token dark_colors dark_colorscheme dark_gui_colorscheme
@ -11410,6 +11411,7 @@ set_ne persistent_command 0
set_ne intuitive_interface 1
set_ne use_cursor_for_selection 0
set_ne autotrim_wires 0
set_ne auto_set_wire_bus 0
set_ne cadence_compat 0
set_ne infix_interface 1
set_ne snap_cursor 0

View File

@ -249,6 +249,10 @@
#### default: 0
# set autotrim_wires 0
#### if set automatically set bus attribute of wires from their names
#### default: 0
# set auto_set_wire_bus 1
#### do not ask to save file when doing control-s or File -> Save
#### default: disabled (0), will ask before saving.
# set no_ask_save 1