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if xschem is started with -n (netlist) load_schematic will not call tcl proc is_xschem_file to determine if sch or sym type, since command line option has higher priority. reverted back possibility in update_symbol() to have double quotes around name attribute (name="My strange name"). This has toooo many implications everywhere. name attribute must be wihout double quotes, xschem will strip them off if any.

This commit is contained in:
Stefan Schippers 2020-10-17 02:54:42 +02:00
parent 0f94bee28e
commit 8a45e319c9
6 changed files with 86 additions and 95 deletions
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28
src/editprop.c
View File

@ -920,8 +920,7 @@ void update_symbol(const char *result, int x)
char *name = NULL, *ptr = NULL, *new_prop = NULL; char *name = NULL, *ptr = NULL, *new_prop = NULL;
char symbol[PATH_MAX]; char symbol[PATH_MAX];
char *type; char *type;
const char *new_name; int cond;
int cond, allow_change_name;
int pushed=0; int pushed=0;
dbg(1, "update_symbol(): entering\n"); dbg(1, "update_symbol(): entering\n");
@ -985,13 +984,6 @@ void update_symbol(const char *result, int x)
} }
} }
/* instance name prefix (1st char) changed? --> allow_change_name=1 */
allow_change_name = 0;
if(new_prop) {
my_strdup(88, &name, get_tok_value(xctx->inst[i].prop_ptr, "name", 0));
new_name = get_tok_value(new_prop, "name", 0);
if(!name || new_name[0] != name[0]) allow_change_name = 1;
}
for(k=0;k<lastselected;k++) { for(k=0;k<lastselected;k++) {
dbg(1, "update_symbol(): for k loop: k=%d\n", k); dbg(1, "update_symbol(): for k loop: k=%d\n", k);
if(selectedgroup[k].type!=ELEMENT) continue; if(selectedgroup[k].type!=ELEMENT) continue;
@ -1060,19 +1052,13 @@ void update_symbol(const char *result, int x)
} }
} }
/* if symbol changed ensure instance name (with new prefix char) is unique */
my_strdup(152, &name, get_tok_value(xctx->inst[i].prop_ptr, "name", 0));
new_name = get_tok_value(xctx->inst[i].prop_ptr, "name", 1); /* retain quotes in name if any */ if(name && name[0] ) {
if(new_name[0]) { dbg(1, "update_symbol(): prefix!='\\0', name=%s\n", name);
if(allow_change_name || (lastselected == 1) ) my_strdup(153, &name, new_name);
/* 20110325 only modify prefix if prefix not NUL */ /* 20110325 only modify prefix if prefix not NUL */
if(prefix) { if(prefix) name[0]=prefix; /* change prefix if changing symbol type; */
if(name[0] != '"') dbg(1, "update_symbol(): name=%s, xctx->inst[i].prop_ptr=%s\n", name, xctx->inst[i].prop_ptr);
name[0]=prefix; /* change prefix if changing symbol type; */
else
name[1]=prefix; /* change prefix if changing symbol type; */
}
dbg(1, "update_symbol(): name=%s, inst[i].prop_ptr=%s\n", name, xctx->inst[i].prop_ptr);
my_strdup(89, &ptr,subst_token(xctx->inst[i].prop_ptr, "name", name) ); my_strdup(89, &ptr,subst_token(xctx->inst[i].prop_ptr, "name", name) );
/* set name of current inst */ /* set name of current inst */

10
src/xinit.c
View File

@ -1444,15 +1444,19 @@ int Tcl_AppInit(Tcl_Interp *inter)
#endif #endif
dbg(1, "Tcl_AppInit(): filename %s given, removing symbols\n", filename); dbg(1, "Tcl_AppInit(): filename %s given, removing symbols\n", filename);
remove_symbols(); remove_symbols();
load_schematic(1, f, 1); /* if do_netlist=1 call load_schematic with 'reset_undo=0' avoiding call
Tcl_VarEval(interp, "update_recent_file {", filename, "}", NULL); to tcl is_xschem_file that could change netlist_type to symbol */
load_schematic(1, f, !do_netlist);
Tcl_VarEval(interp, "update_recent_file {", f, "}", NULL);
} else { } else {
char * tmp; char * tmp;
char filename[PATH_MAX]; char filename[PATH_MAX];
tmp = (char *) tclgetvar("XSCHEM_START_WINDOW"); tmp = (char *) tclgetvar("XSCHEM_START_WINDOW");
dbg(1, "Tcl_AppInit(): tmp=%s\n", tmp? tmp: "NULL"); dbg(1, "Tcl_AppInit(): tmp=%s\n", tmp? tmp: "NULL");
my_strncpy(filename, abs_sym_path(tmp, ""), S(filename)); my_strncpy(filename, abs_sym_path(tmp, ""), S(filename));
load_schematic(1, filename, 1); /* if do_netlist=1 call load_schematic with 'reset_undo=0' avoiding call
to tcl is_xschem_file that could change netlist_type to symbol */
load_schematic(1, filename, !do_netlist);
} }

8
xschem_library/devices/diode.sym
View File

@ -12,9 +12,9 @@ L 4 -10 5 10 5 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1} B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2} B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
P 4 4 -0 5 -10 -5 10 -5 0 5 {fill=true} P 4 4 -0 5 -10 -5 10 -5 0 5 {fill=true}
T {@name} 2.5 -20 0 0 0.2 0.2 {}
T {@model} 5 12.5 0 0 0.25 0.2 {}
T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13} T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13} T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13}
T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15} T {@name} 15 -18.75 0 0 0.2 0.2 {}
T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15} T {@model} 15 -6.25 0 0 0.2 0.2 {}
T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}

16
xschem_library/devices/pnp.sym
View File

@ -20,11 +20,11 @@ B 5 17.5 27.5 22.5 32.5 {name=C dir=inout pinnumber=3}
B 5 -22.5 -2.5 -17.5 2.5 {name=B dir=in pinnumber=1} B 5 -22.5 -2.5 -17.5 2.5 {name=B dir=in pinnumber=1}
B 5 17.5 -32.5 22.5 -27.5 {name=E dir=inout pinnumber=2} B 5 17.5 -32.5 22.5 -27.5 {name=E dir=inout pinnumber=2}
P 4 4 0 -10 15 -15 5 -25 0 -10 {fill=true} P 4 4 0 -10 15 -15 5 -25 0 -10 {fill=true}
T {@model} 20 -13.75 0 0 0.2 0.2 {} T {@model} 20 -12.5 0 0 0.2 0.2 {}
T {@name} 20 1.25 0 0 0.2 0.2 {} T {@name} 20 0 0 0 0.2 0.2 {}
T {@#2:pinnumber} 25 -28.75 0 0 0.2 0.2 {layer=13} T {@#2:pinnumber} 25 -25 0 0 0.2 0.2 {layer=13}
T {@#0:pinnumber} 25 17.5 0 0 0.2 0.2 {layer=13} T {@#0:pinnumber} 25 12.5 0 0 0.2 0.2 {layer=13}
T {@#1:pinnumber} -11.25 6.25 0 1 0.2 0.2 {layer=13} T {@#1:pinnumber} -5 6.25 0 1 0.2 0.2 {layer=13}
T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15} T {@#2:net_name} 25 -33.75 0 0 0.15 0.15 {layer=15}
T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15} T {@#0:net_name} 25 23.75 0 0 0.15 0.15 {layer=15}
T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15} T {@#1:net_name} -6.25 -12.5 0 1 0.15 0.15 {layer=15}

8
xschem_library/devices/zener.sym
View File

@ -16,9 +16,9 @@ L 4 -20 5 -20 15 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1} B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2} B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
P 4 4 -0 5 -10 -5 10 -5 -0 5 {fill=true} P 4 4 -0 5 -10 -5 10 -5 -0 5 {fill=true}
T {@name} 2.5 -20 0 0 0.2 0.2 {}
T {@model} 2.5 12.5 0 0 0.2 0.2 {}
T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13} T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13} T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13}
T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15} T {@name} 15 -18.75 0 0 0.2 0.2 {}
T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15} T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
T {@model} 15 6.25 0 0 0.2 0.2 {}

111
xschem_library/examples/TwoStageAmp.sch
View File

@ -1,5 +1,6 @@
v {xschem version=2.9.5_RC6 file_version=1.1} v {xschem version=2.9.8 file_version=1.2}
G {} G {}
K {}
V {} V {}
S {} S {}
E {} E {}
@ -41,118 +42,118 @@ N 760 -190 760 -170 {lab=VCC}
N 710 -580 730 -580 {lab=Vbase2} N 710 -580 730 -580 {lab=Vbase2}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"} C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {vsource.sym} 90 -290 0 0 {name=Vinput C {vsource.sym} 90 -290 0 0 {name=Vinput
value="DC 1.6V AC 1 0 SIN(0 1MV 1KHZ)"} value="DC 1.6V AC 1 0 SIN(0 1MV 1KHZ)" net_name=true}
C {gnd.sym} 90 -260 0 0 {name=l2 lab=0} C {gnd.sym} 90 -260 0 0 {name=l2 lab=0 net_name=true}
C {res.sym} 150 -460 3 1 {name=R5 C {res.sym} 150 -460 3 1 {name=R5
value=10 value=10
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {capa.sym} 250 -460 3 1 {name=C1 C {capa.sym} 250 -460 3 1 {name=C1
m=1 m=1
value=2.2u value=2.2u
footprint=1206 footprint=1206
device="ceramic capacitor"} device="ceramic capacitor" net_name=true}
C {res.sym} 310 -550 0 0 {name=R1 C {res.sym} 310 -550 0 0 {name=R1
value=28K value=28K
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {res.sym} 330 -290 0 0 {name=R2 C {res.sym} 330 -290 0 0 {name=R2
value=2K value=2K
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {gnd.sym} 330 -260 0 0 {name=l3 lab=0} C {gnd.sym} 330 -260 0 0 {name=l3 lab=0 net_name=true}
C {npn.sym} 410 -460 0 0 {name=Q1 C {npn.sym} 410 -460 0 0 {name=Q1
model=Q2N3904 model=Q2N3904
device=2N3904 device=2N3904
footprint=TO92 footprint=TO92
area=1 area=1
pinnumber(1) = 2 ; "alternatively use pinnumber(B)" pinnumber(1) = 2 ; "alternatively use pinnumber(B)"
pinnumber(2) = 1 ; "alternatively use pinnumber(E)"} pinnumber(2) = 1 ; "alternatively use pinnumber(E)" net_name=true}
C {res.sym} 430 -290 0 0 {name=RE1 C {res.sym} 430 -290 0 0 {name=RE1
value=100 value=100
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {gnd.sym} 430 -260 0 0 {name=l4 lab=0} C {gnd.sym} 430 -260 0 0 {name=l4 lab=0 net_name=true}
C {capa.sym} 510 -290 0 0 {name=CE1 C {capa.sym} 510 -290 0 0 {name=CE1
m=1 m=1
value=1p value=1p
footprint=1206 footprint=1206
device="ceramic capacitor"} device="ceramic capacitor" net_name=true}
C {gnd.sym} 510 -260 0 0 {name=l5 lab=0} C {gnd.sym} 510 -260 0 0 {name=l5 lab=0 net_name=true}
C {res.sym} 430 -700 0 0 {name=RC1 C {res.sym} 430 -700 0 0 {name=RC1
value=3.3K value=3.3K
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {vdd.sym} 430 -730 0 0 {name=l6 lab=VCC} C {vdd.sym} 430 -730 0 0 {name=l6 lab=VCC net_name=true}
C {vdd.sym} 310 -580 0 0 {name=l7 lab=VCC} C {vdd.sym} 310 -580 0 0 {name=l7 lab=VCC net_name=true}
C {ipin.sym} 70 -460 0 0 {name=p1 lab=Vin} C {ipin.sym} 70 -460 0 0 {name=p1 lab=Vin net_name=true}
C {res.sym} 500 -580 3 1 {name=R8 C {res.sym} 500 -580 3 1 {name=R8
value=1 value=1
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {capa.sym} 600 -580 3 1 {name=C2 C {capa.sym} 600 -580 3 1 {name=C2
m=1 m=1
value=2.2u value=2.2u
footprint=1206 footprint=1206
device="ceramic capacitor"} device="ceramic capacitor" net_name=true}
C {res.sym} 690 -700 0 0 {name=R3 C {res.sym} 690 -700 0 0 {name=R3
value=28K value=28K
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {res.sym} 710 -490 0 0 {name=R4 C {res.sym} 710 -490 0 0 {name=R4
value=2.8K value=2.8K
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {gnd.sym} 710 -460 0 0 {name=l8 lab=0} C {gnd.sym} 710 -460 0 0 {name=l8 lab=0 net_name=true}
C {vdd.sym} 690 -730 0 0 {name=l9 lab=VCC} C {vdd.sym} 690 -730 0 0 {name=l9 lab=VCC net_name=true}
C {npn.sym} 820 -580 0 0 {name=Q2 C {npn.sym} 820 -580 0 0 {name=Q2
model=Q2N3904 model=Q2N3904
device=2N3904 device=2N3904
footprint=TO92 footprint=TO92
area=1 area=1
pinnumber(1) = 2 pinnumber(1) = 2
pinnumber(2) = 1} pinnumber(2) = 1 net_name=true}
C {res.sym} 840 -700 0 0 {name=RC2 C {res.sym} 840 -700 0 0 {name=RC2
value=1K value=1K
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {vdd.sym} 840 -730 0 0 {name=l10 lab=VCC} C {vdd.sym} 840 -730 0 0 {name=l10 lab=VCC net_name=true}
C {res.sym} 840 -290 0 0 {name=RE2 C {res.sym} 840 -290 0 0 {name=RE2
value=100 value=100
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {gnd.sym} 840 -260 0 0 {name=l11 lab=0} C {gnd.sym} 840 -260 0 0 {name=l11 lab=0 net_name=true}
C {capa.sym} 920 -290 0 0 {name=CE2 C {capa.sym} 920 -290 0 0 {name=CE2
m=1 m=1
value=1p value=1p
footprint=1206 footprint=1206
device="ceramic capacitor"} device="ceramic capacitor" net_name=true}
C {gnd.sym} 920 -260 0 0 {name=l12 lab=0} C {gnd.sym} 920 -260 0 0 {name=l12 lab=0 net_name=true}
C {capa.sym} 950 -630 3 1 {name=Cout C {capa.sym} 950 -630 3 1 {name=Cout
m=1 m=1
value=2.2u value=2.2u
footprint=1206 footprint=1206
device="ceramic capacitor"} device="ceramic capacitor" net_name=true}
C {res.sym} 1000 -490 0 0 {name=RL C {res.sym} 1000 -490 0 0 {name=RL
value=100K value=100K
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1 net_name=true}
C {gnd.sym} 1000 -460 0 0 {name=l13 lab=0} C {gnd.sym} 1000 -460 0 0 {name=l13 lab=0 net_name=true}
C {opin.sym} 1050 -630 0 0 {name=p2 lab=Vout} C {opin.sym} 1050 -630 0 0 {name=p2 lab=Vout net_name=true}
C {vdd.sym} 760 -190 0 0 {name=l14 lab=VCC} C {vdd.sym} 760 -190 0 0 {name=l14 lab=VCC net_name=true}
C {vsource.sym} 760 -140 0 0 {name=VCC value=15} C {vsource.sym} 760 -140 0 0 {name=VCC value=15 net_name=true}
C {gnd.sym} 760 -110 0 0 {name=l15 lab=0} C {gnd.sym} 760 -110 0 0 {name=l15 lab=0 net_name=true}
C {code.sym} 160 -190 0 0 {name=MODELS value=".model Q2N3904 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 C {code.sym} 160 -190 0 0 {name=MODELS value=".model Q2N3904 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259
+ Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 + Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1
+ Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 + Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75
@ -168,21 +169,21 @@ value=".SAVE ALL
* .DC Vinput 0 5 .01 * .DC Vinput 0 5 .01
* .DC Vinput 1 2 .0 * .DC Vinput 1 2 .0
"} "}
C {spice_probe.sym} 1020 -630 0 0 {name=p3 analysis=tran voltage=0.0000e+00} C {spice_probe.sym} 1020 -630 0 0 {name=p3 analysis=tran voltage=0.0000e+00 net_name=true}
C {spice_probe.sym} 650 -580 0 0 {name=p4 analysis=tran voltage=1.28} C {spice_probe.sym} 650 -580 0 0 {name=p4 analysis=tran voltage=1.28 net_name=true}
C {spice_probe.sym} 840 -500 0 0 {name=p5 analysis=tran voltage=0.5705} C {spice_probe.sym} 840 -500 0 0 {name=p5 analysis=tran voltage=0.5705 net_name=true}
C {spice_probe.sym} 430 -540 0 1 {name=p6 analysis=tran voltage=5.932} C {spice_probe.sym} 430 -540 0 1 {name=p6 analysis=tran voltage=5.932 net_name=true}
C {spice_probe.sym} 360 -460 0 1 {name=p7 analysis=tran voltage=0.9675} C {spice_probe.sym} 360 -460 0 1 {name=p7 analysis=tran voltage=0.9675 net_name=true}
C {spice_probe.sym} 110 -460 0 1 {name=p8 analysis=tran voltage=1.6} C {spice_probe.sym} 110 -460 0 1 {name=p8 analysis=tran voltage=1.6 net_name=true}
C {spice_probe.sym} 880 -630 0 0 {name=p9 analysis=tran voltage=9.328} C {spice_probe.sym} 880 -630 0 0 {name=p9 analysis=tran voltage=9.328 net_name=true}
C {lab_pin.sym} 430 -650 0 0 {name=l16 sig_type=std_logic lab=Vcoll1} C {lab_pin.sym} 430 -650 0 0 {name=l16 sig_type=std_logic lab=Vcoll1 net_name=true}
C {lab_pin.sym} 840 -650 0 0 {name=l17 sig_type=std_logic lab=Vcoll2} C {lab_pin.sym} 840 -650 0 0 {name=l17 sig_type=std_logic lab=Vcoll2 net_name=true}
C {lab_pin.sym} 710 -550 0 0 {name=l18 sig_type=std_logic lab=Vbase2} C {lab_pin.sym} 710 -550 0 0 {name=l18 sig_type=std_logic lab=Vbase2 net_name=true}
C {lab_pin.sym} 310 -510 0 0 {name=l19 sig_type=std_logic lab=Vbase1} C {lab_pin.sym} 310 -510 0 0 {name=l19 sig_type=std_logic lab=Vbase1 net_name=true}
C {lab_pin.sym} 840 -420 0 0 {name=l20 sig_type=std_logic lab=Vem2} C {lab_pin.sym} 840 -420 0 0 {name=l20 sig_type=std_logic lab=Vem2 net_name=true}
C {lab_pin.sym} 430 -420 0 0 {name=l21 sig_type=std_logic lab=Vem1} C {lab_pin.sym} 430 -420 0 0 {name=l21 sig_type=std_logic lab=Vem1 net_name=true}
C {ammeter.sym} 840 -450 0 0 {name=vm2 current=0.005705} C {ammeter.sym} 840 -450 0 0 {name=vm2 current=0.005705 net_name=true}
C {ammeter.sym} 430 -370 0 0 {name=vm1 current=0.002765} C {ammeter.sym} 430 -370 0 0 {name=vm1 current=0.002765 net_name=true}
C {spice_probe.sym} 510 -330 0 0 {name=p10 analysis=tran voltage=0.2765} C {spice_probe.sym} 510 -330 0 0 {name=p10 analysis=tran voltage=0.2765 net_name=true}
C {spice_probe.sym} 760 -170 0 1 {name=p12 analysis=tran voltage=15} C {spice_probe.sym} 760 -170 0 1 {name=p12 analysis=tran voltage=15 net_name=true}
C {ammeter.sym} 760 -580 3 0 {name=v1 current=3.2742e-05} C {ammeter.sym} 760 -580 3 0 {name=v1 current=3.2742e-05 net_name=true}