if xschem is started with -n (netlist) load_schematic will not call tcl proc is_xschem_file to determine if sch or sym type, since command line option has higher priority. reverted back possibility in update_symbol() to have double quotes around name attribute (name="My strange name"). This has toooo many implications everywhere. name attribute must be wihout double quotes, xschem will strip them off if any.
This commit is contained in:
Stefan Schippers
parent
0f94bee28e
commit
8a45e319c9
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@ -920,8 +920,7 @@ void update_symbol(const char *result, int x)
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char *name = NULL, *ptr = NULL, *new_prop = NULL;
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char symbol[PATH_MAX];
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char *type;
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const char *new_name;
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int cond, allow_change_name;
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int cond;
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int pushed=0;
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dbg(1, "update_symbol(): entering\n");
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@ -985,13 +984,6 @@ void update_symbol(const char *result, int x)
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}
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}
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/* instance name prefix (1st char) changed? --> allow_change_name=1 */
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allow_change_name = 0;
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if(new_prop) {
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my_strdup(88, &name, get_tok_value(xctx->inst[i].prop_ptr, "name", 0));
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new_name = get_tok_value(new_prop, "name", 0);
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if(!name || new_name[0] != name[0]) allow_change_name = 1;
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}
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for(k=0;k<lastselected;k++) {
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dbg(1, "update_symbol(): for k loop: k=%d\n", k);
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if(selectedgroup[k].type!=ELEMENT) continue;
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@ -1060,19 +1052,13 @@ void update_symbol(const char *result, int x)
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}
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}
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new_name = get_tok_value(xctx->inst[i].prop_ptr, "name", 1); /* retain quotes in name if any */
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if(new_name[0]) {
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if(allow_change_name || (lastselected == 1) ) my_strdup(153, &name, new_name);
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/* if symbol changed ensure instance name (with new prefix char) is unique */
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my_strdup(152, &name, get_tok_value(xctx->inst[i].prop_ptr, "name", 0));
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if(name && name[0] ) {
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dbg(1, "update_symbol(): prefix!='\\0', name=%s\n", name);
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/* 20110325 only modify prefix if prefix not NUL */
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if(prefix) {
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if(name[0] != '"')
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name[0]=prefix; /* change prefix if changing symbol type; */
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else
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name[1]=prefix; /* change prefix if changing symbol type; */
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}
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dbg(1, "update_symbol(): name=%s, inst[i].prop_ptr=%s\n", name, xctx->inst[i].prop_ptr);
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if(prefix) name[0]=prefix; /* change prefix if changing symbol type; */
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dbg(1, "update_symbol(): name=%s, xctx->inst[i].prop_ptr=%s\n", name, xctx->inst[i].prop_ptr);
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my_strdup(89, &ptr,subst_token(xctx->inst[i].prop_ptr, "name", name) );
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/* set name of current inst */
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10
src/xinit.c
10
src/xinit.c
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@ -1444,15 +1444,19 @@ int Tcl_AppInit(Tcl_Interp *inter)
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#endif
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dbg(1, "Tcl_AppInit(): filename %s given, removing symbols\n", filename);
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remove_symbols();
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load_schematic(1, f, 1);
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Tcl_VarEval(interp, "update_recent_file {", filename, "}", NULL);
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/* if do_netlist=1 call load_schematic with 'reset_undo=0' avoiding call
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to tcl is_xschem_file that could change netlist_type to symbol */
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load_schematic(1, f, !do_netlist);
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Tcl_VarEval(interp, "update_recent_file {", f, "}", NULL);
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} else {
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char * tmp;
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char filename[PATH_MAX];
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tmp = (char *) tclgetvar("XSCHEM_START_WINDOW");
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dbg(1, "Tcl_AppInit(): tmp=%s\n", tmp? tmp: "NULL");
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my_strncpy(filename, abs_sym_path(tmp, ""), S(filename));
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load_schematic(1, filename, 1);
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/* if do_netlist=1 call load_schematic with 'reset_undo=0' avoiding call
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to tcl is_xschem_file that could change netlist_type to symbol */
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load_schematic(1, filename, !do_netlist);
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}
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@ -12,9 +12,9 @@ L 4 -10 5 10 5 {}
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B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
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B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
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P 4 4 -0 5 -10 -5 10 -5 0 5 {fill=true}
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T {@name} 2.5 -20 0 0 0.2 0.2 {}
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T {@model} 5 12.5 0 0 0.25 0.2 {}
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T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13}
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T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
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T {@name} 15 -18.75 0 0 0.2 0.2 {}
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T {@model} 15 -6.25 0 0 0.2 0.2 {}
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T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
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@ -20,11 +20,11 @@ B 5 17.5 27.5 22.5 32.5 {name=C dir=inout pinnumber=3}
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B 5 -22.5 -2.5 -17.5 2.5 {name=B dir=in pinnumber=1}
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B 5 17.5 -32.5 22.5 -27.5 {name=E dir=inout pinnumber=2}
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P 4 4 0 -10 15 -15 5 -25 0 -10 {fill=true}
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T {@model} 20 -13.75 0 0 0.2 0.2 {}
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T {@name} 20 1.25 0 0 0.2 0.2 {}
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T {@#2:pinnumber} 25 -28.75 0 0 0.2 0.2 {layer=13}
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T {@#0:pinnumber} 25 17.5 0 0 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -11.25 6.25 0 1 0.2 0.2 {layer=13}
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T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
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T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
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T {@model} 20 -12.5 0 0 0.2 0.2 {}
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T {@name} 20 0 0 0 0.2 0.2 {}
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T {@#2:pinnumber} 25 -25 0 0 0.2 0.2 {layer=13}
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T {@#0:pinnumber} 25 12.5 0 0 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -5 6.25 0 1 0.2 0.2 {layer=13}
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T {@#2:net_name} 25 -33.75 0 0 0.15 0.15 {layer=15}
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T {@#0:net_name} 25 23.75 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} -6.25 -12.5 0 1 0.15 0.15 {layer=15}
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@ -16,9 +16,9 @@ L 4 -20 5 -20 15 {}
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B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
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B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
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P 4 4 -0 5 -10 -5 10 -5 -0 5 {fill=true}
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T {@name} 2.5 -20 0 0 0.2 0.2 {}
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T {@model} 2.5 12.5 0 0 0.2 0.2 {}
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T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13}
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T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
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T {@name} 15 -18.75 0 0 0.2 0.2 {}
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T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
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T {@model} 15 6.25 0 0 0.2 0.2 {}
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@ -1,5 +1,6 @@
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v {xschem version=2.9.5_RC6 file_version=1.1}
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v {xschem version=2.9.8 file_version=1.2}
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G {}
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K {}
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V {}
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S {}
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E {}
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@ -41,118 +42,118 @@ N 760 -190 760 -170 {lab=VCC}
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N 710 -580 730 -580 {lab=Vbase2}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {vsource.sym} 90 -290 0 0 {name=Vinput
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value="DC 1.6V AC 1 0 SIN(0 1MV 1KHZ)"}
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C {gnd.sym} 90 -260 0 0 {name=l2 lab=0}
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value="DC 1.6V AC 1 0 SIN(0 1MV 1KHZ)" net_name=true}
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C {gnd.sym} 90 -260 0 0 {name=l2 lab=0 net_name=true}
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C {res.sym} 150 -460 3 1 {name=R5
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value=10
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footprint=1206
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device=resistor
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m=1}
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m=1 net_name=true}
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C {capa.sym} 250 -460 3 1 {name=C1
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m=1
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value=2.2u
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footprint=1206
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device="ceramic capacitor"}
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device="ceramic capacitor" net_name=true}
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C {res.sym} 310 -550 0 0 {name=R1
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value=28K
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footprint=1206
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device=resistor
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m=1}
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m=1 net_name=true}
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C {res.sym} 330 -290 0 0 {name=R2
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value=2K
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footprint=1206
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device=resistor
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m=1}
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C {gnd.sym} 330 -260 0 0 {name=l3 lab=0}
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m=1 net_name=true}
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C {gnd.sym} 330 -260 0 0 {name=l3 lab=0 net_name=true}
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C {npn.sym} 410 -460 0 0 {name=Q1
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model=Q2N3904
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device=2N3904
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footprint=TO92
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area=1
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pinnumber(1) = 2 ; "alternatively use pinnumber(B)"
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pinnumber(2) = 1 ; "alternatively use pinnumber(E)"}
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pinnumber(2) = 1 ; "alternatively use pinnumber(E)" net_name=true}
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C {res.sym} 430 -290 0 0 {name=RE1
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value=100
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footprint=1206
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device=resistor
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m=1}
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C {gnd.sym} 430 -260 0 0 {name=l4 lab=0}
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m=1 net_name=true}
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C {gnd.sym} 430 -260 0 0 {name=l4 lab=0 net_name=true}
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C {capa.sym} 510 -290 0 0 {name=CE1
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m=1
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value=1p
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footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 510 -260 0 0 {name=l5 lab=0}
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device="ceramic capacitor" net_name=true}
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C {gnd.sym} 510 -260 0 0 {name=l5 lab=0 net_name=true}
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C {res.sym} 430 -700 0 0 {name=RC1
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value=3.3K
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footprint=1206
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device=resistor
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m=1}
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C {vdd.sym} 430 -730 0 0 {name=l6 lab=VCC}
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C {vdd.sym} 310 -580 0 0 {name=l7 lab=VCC}
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C {ipin.sym} 70 -460 0 0 {name=p1 lab=Vin}
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m=1 net_name=true}
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C {vdd.sym} 430 -730 0 0 {name=l6 lab=VCC net_name=true}
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C {vdd.sym} 310 -580 0 0 {name=l7 lab=VCC net_name=true}
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C {ipin.sym} 70 -460 0 0 {name=p1 lab=Vin net_name=true}
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C {res.sym} 500 -580 3 1 {name=R8
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value=1
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footprint=1206
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device=resistor
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m=1}
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m=1 net_name=true}
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C {capa.sym} 600 -580 3 1 {name=C2
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m=1
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value=2.2u
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footprint=1206
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device="ceramic capacitor"}
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device="ceramic capacitor" net_name=true}
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C {res.sym} 690 -700 0 0 {name=R3
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value=28K
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footprint=1206
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device=resistor
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m=1}
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m=1 net_name=true}
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C {res.sym} 710 -490 0 0 {name=R4
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value=2.8K
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footprint=1206
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device=resistor
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m=1}
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C {gnd.sym} 710 -460 0 0 {name=l8 lab=0}
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C {vdd.sym} 690 -730 0 0 {name=l9 lab=VCC}
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m=1 net_name=true}
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C {gnd.sym} 710 -460 0 0 {name=l8 lab=0 net_name=true}
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C {vdd.sym} 690 -730 0 0 {name=l9 lab=VCC net_name=true}
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C {npn.sym} 820 -580 0 0 {name=Q2
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model=Q2N3904
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device=2N3904
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footprint=TO92
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area=1
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pinnumber(1) = 2
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pinnumber(2) = 1}
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pinnumber(2) = 1 net_name=true}
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C {res.sym} 840 -700 0 0 {name=RC2
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value=1K
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footprint=1206
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device=resistor
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m=1}
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C {vdd.sym} 840 -730 0 0 {name=l10 lab=VCC}
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m=1 net_name=true}
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C {vdd.sym} 840 -730 0 0 {name=l10 lab=VCC net_name=true}
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C {res.sym} 840 -290 0 0 {name=RE2
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value=100
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footprint=1206
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device=resistor
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m=1}
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C {gnd.sym} 840 -260 0 0 {name=l11 lab=0}
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m=1 net_name=true}
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C {gnd.sym} 840 -260 0 0 {name=l11 lab=0 net_name=true}
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C {capa.sym} 920 -290 0 0 {name=CE2
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m=1
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value=1p
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footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 920 -260 0 0 {name=l12 lab=0}
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device="ceramic capacitor" net_name=true}
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C {gnd.sym} 920 -260 0 0 {name=l12 lab=0 net_name=true}
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C {capa.sym} 950 -630 3 1 {name=Cout
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m=1
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value=2.2u
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footprint=1206
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device="ceramic capacitor"}
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device="ceramic capacitor" net_name=true}
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C {res.sym} 1000 -490 0 0 {name=RL
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value=100K
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footprint=1206
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device=resistor
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m=1}
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C {gnd.sym} 1000 -460 0 0 {name=l13 lab=0}
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C {opin.sym} 1050 -630 0 0 {name=p2 lab=Vout}
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C {vdd.sym} 760 -190 0 0 {name=l14 lab=VCC}
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C {vsource.sym} 760 -140 0 0 {name=VCC value=15}
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C {gnd.sym} 760 -110 0 0 {name=l15 lab=0}
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m=1 net_name=true}
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C {gnd.sym} 1000 -460 0 0 {name=l13 lab=0 net_name=true}
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C {opin.sym} 1050 -630 0 0 {name=p2 lab=Vout net_name=true}
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C {vdd.sym} 760 -190 0 0 {name=l14 lab=VCC net_name=true}
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C {vsource.sym} 760 -140 0 0 {name=VCC value=15 net_name=true}
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C {gnd.sym} 760 -110 0 0 {name=l15 lab=0 net_name=true}
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C {code.sym} 160 -190 0 0 {name=MODELS value=".model Q2N3904 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259
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+ Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1
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+ Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75
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@ -168,21 +169,21 @@ value=".SAVE ALL
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* .DC Vinput 0 5 .01
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* .DC Vinput 1 2 .0
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"}
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C {spice_probe.sym} 1020 -630 0 0 {name=p3 analysis=tran voltage=0.0000e+00}
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C {spice_probe.sym} 650 -580 0 0 {name=p4 analysis=tran voltage=1.28}
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C {spice_probe.sym} 840 -500 0 0 {name=p5 analysis=tran voltage=0.5705}
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C {spice_probe.sym} 430 -540 0 1 {name=p6 analysis=tran voltage=5.932}
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C {spice_probe.sym} 360 -460 0 1 {name=p7 analysis=tran voltage=0.9675}
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C {spice_probe.sym} 110 -460 0 1 {name=p8 analysis=tran voltage=1.6}
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C {spice_probe.sym} 880 -630 0 0 {name=p9 analysis=tran voltage=9.328}
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C {lab_pin.sym} 430 -650 0 0 {name=l16 sig_type=std_logic lab=Vcoll1}
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C {lab_pin.sym} 840 -650 0 0 {name=l17 sig_type=std_logic lab=Vcoll2}
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C {lab_pin.sym} 710 -550 0 0 {name=l18 sig_type=std_logic lab=Vbase2}
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C {lab_pin.sym} 310 -510 0 0 {name=l19 sig_type=std_logic lab=Vbase1}
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C {lab_pin.sym} 840 -420 0 0 {name=l20 sig_type=std_logic lab=Vem2}
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C {lab_pin.sym} 430 -420 0 0 {name=l21 sig_type=std_logic lab=Vem1}
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C {ammeter.sym} 840 -450 0 0 {name=vm2 current=0.005705}
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C {ammeter.sym} 430 -370 0 0 {name=vm1 current=0.002765}
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C {spice_probe.sym} 510 -330 0 0 {name=p10 analysis=tran voltage=0.2765}
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C {spice_probe.sym} 760 -170 0 1 {name=p12 analysis=tran voltage=15}
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C {ammeter.sym} 760 -580 3 0 {name=v1 current=3.2742e-05}
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C {spice_probe.sym} 1020 -630 0 0 {name=p3 analysis=tran voltage=0.0000e+00 net_name=true}
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C {spice_probe.sym} 650 -580 0 0 {name=p4 analysis=tran voltage=1.28 net_name=true}
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C {spice_probe.sym} 840 -500 0 0 {name=p5 analysis=tran voltage=0.5705 net_name=true}
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C {spice_probe.sym} 430 -540 0 1 {name=p6 analysis=tran voltage=5.932 net_name=true}
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C {spice_probe.sym} 360 -460 0 1 {name=p7 analysis=tran voltage=0.9675 net_name=true}
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C {spice_probe.sym} 110 -460 0 1 {name=p8 analysis=tran voltage=1.6 net_name=true}
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C {spice_probe.sym} 880 -630 0 0 {name=p9 analysis=tran voltage=9.328 net_name=true}
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C {lab_pin.sym} 430 -650 0 0 {name=l16 sig_type=std_logic lab=Vcoll1 net_name=true}
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C {lab_pin.sym} 840 -650 0 0 {name=l17 sig_type=std_logic lab=Vcoll2 net_name=true}
|
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C {lab_pin.sym} 710 -550 0 0 {name=l18 sig_type=std_logic lab=Vbase2 net_name=true}
|
||||
C {lab_pin.sym} 310 -510 0 0 {name=l19 sig_type=std_logic lab=Vbase1 net_name=true}
|
||||
C {lab_pin.sym} 840 -420 0 0 {name=l20 sig_type=std_logic lab=Vem2 net_name=true}
|
||||
C {lab_pin.sym} 430 -420 0 0 {name=l21 sig_type=std_logic lab=Vem1 net_name=true}
|
||||
C {ammeter.sym} 840 -450 0 0 {name=vm2 current=0.005705 net_name=true}
|
||||
C {ammeter.sym} 430 -370 0 0 {name=vm1 current=0.002765 net_name=true}
|
||||
C {spice_probe.sym} 510 -330 0 0 {name=p10 analysis=tran voltage=0.2765 net_name=true}
|
||||
C {spice_probe.sym} 760 -170 0 1 {name=p12 analysis=tran voltage=15 net_name=true}
|
||||
C {ammeter.sym} 760 -580 3 0 {name=v1 current=3.2742e-05 net_name=true}
|
||||
|
|
|
|||
Loading…
Reference in New Issue