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command "xschem change_elem_order" invalidate inst/wire hashes and connectivity to force consistency

This commit is contained in:
stefan schippers 2023-09-17 09:45:28 +02:00
parent 159f07e703
commit 898cfcc2e1
2 changed files with 9 additions and 3 deletions
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2
doc/xschem_man/developer_info.html
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@ -948,7 +948,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
if no 'attr' is given return full attribute string,
else return value for attribute 'attr'.
Example: xschem pinlist x3 name
--> { {0} {PLUS} } { {1} {OUT} } { {2} {{MINUS} }
--> { {0} {PLUS} } { {1} {OUT} } { {2} {MINUS} }
Example: xschem pinlist x3 dir
--> { {0} {in} } { {1} {out} } { {2} {in} }
Example: xschem pinlist x3

10
src/scheduler.c
View File

@ -372,7 +372,13 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
{
if(argc > 2) {
int n = atoi(argv[2]);
if(n >= 0) change_elem_order(n);
if(n >= 0) {
change_elem_order(n);
xctx->prep_hash_wires=0;
xctx->prep_hash_inst=0;
xctx->prep_net_structs=0;
xctx->prep_hi_structs=0;
}
}
}
@ -2535,7 +2541,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
* if no 'attr' is given return full attribute string,
* else return value for attribute 'attr'.
* Example: xschem pinlist x3 name
* --> { {0} {PLUS} } { {1} {OUT} } { {2} {{MINUS} }
* --> { {0} {PLUS} } { {1} {OUT} } { {2} {MINUS} }
* Example: xschem pinlist x3 dir
* --> { {0} {in} } { {1} {out} } { {2} {in} }
* Example: xschem pinlist x3