ipdated examples/poweramp_lcc.sch
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v {xschem version=3.4.5 file_version=1.2
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v {xschem version=3.4.6RC file_version=1.2
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*
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*
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* This file is part of XSCHEM,
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -38,8 +38,8 @@ B 2 2520 -210 3200 -20 {flags=graph
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y1 = -0.0035
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y1 = -0.0035
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y2 = 11
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y2 = 11
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divy = 6
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divy = 6
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x1=0.0176314
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x1=0.0097330137
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x2=0.0183299
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x2=0.010324865
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divx=10
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divx=10
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node="i(v.x1.vu)
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node="i(v.x1.vu)
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i(v.x0.vu)
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i(v.x0.vu)
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@ -51,8 +51,8 @@ B 2 2520 -540 3200 -230 {flags=graph
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y1 = -49
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y1 = -49
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y2 = 59
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y2 = 59
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divy = 12
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divy = 12
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x1=0.0176314
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x1=0.0097330137
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x2=0.0183299
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x2=0.010324865
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divx=10
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divx=10
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node="outp
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node="outp
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outm
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outm
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@ -67,8 +67,8 @@ B 2 2520 -730 3200 -540 {flags=graph
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y1 = 0
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y1 = 0
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y2 = 840
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y2 = 840
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divy = 6
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divy = 6
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x1=0.0176314
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x1=0.0097330137
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x2=0.0183299
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x2=0.010324865
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divx=10
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divx=10
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@ -81,8 +81,8 @@ B 2 2520 -20 3200 170 {flags=graph
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y1 = 0
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y1 = 0
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y2 = 850
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y2 = 850
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divy = 6
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divy = 6
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x1=0.0176314
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x1=0.0097330137
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x2=0.0183299
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x2=0.010324865
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divx=10
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divx=10
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@ -348,8 +348,9 @@ vvss vss 0 dc 0
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.control
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.control
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save all
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save all
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op
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op
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write poweramp_lcc_op.raw
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write poweramp_lcc.raw
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tran 8e-7 0.07 uic
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set appendwrite
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tran 8e-7 0.02 uic
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* .FOUR 20k v(outm,outp)
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* .FOUR 20k v(outm,outp)
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* .probe i(*)
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* .probe i(*)
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plot outp outm
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plot outp outm
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