add xschem logic_get command to get logic state of nets

doc/xschem_man/developer_info.html

@@ -480,6 +480,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
         -->
 
 
+
   <li><kbd>       abort_operation</kbd></li><pre>
   Resets UI state, unselect all and abort any pending operation </pre>
   <li><kbd>       add_symbol_pin</kbd></li><pre>
@@ -772,6 +773,9 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
   If 'f' is given output stderr messages to file 'f'
   if 'f' is not given and a file log is open, close log
   file and resume logging to stderr </pre>
+  <li><kbd>       logic_get net_name</kbd></li><pre>
+  Get logic state of net named 'net_name'
+  Returns 0, 1, 2, 3 for logic levels 0, 1, X, Z or nothing if no net found.</pre>
   <li><kbd>       logic_set n num</kbd></li><pre>
   Set selected nets, net labels or pins to logic level 'n' 'num' times.
   'n': 
@@ -781,17 +785,10 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
   3  set to logic value Z
   -1  toggle logic valie (1-&gt;0, 0-&gt;1)
   the 'num' parameter is essentially useful only with 'toggle' (-1)  value</pre>
-  <li><kbd>       logic_set n num</kbd></li><pre>
+  <li><kbd>       make_sch</kbd></li><pre>
-  Set selected nets, net labels or pins to logic level 'n' 'num' times.
+  Make a schematic from selected symbol </pre>
-  'n': 
-  0  set to logic value 0
-  1  set to logic value 1
-  2  set to logic value X
-  3  set to logic value Z
-  -1  toggle logic valie (1-&gt;0, 0-&gt;1)
-  the 'num' parameter is essentially useful only with 'toggle' (-1)  value</pre>
   <li><kbd>       make_sch_from_sel </kbd></li><pre>
-  create an LCC instance from selection and place it instead of selection
+  Create an LCC instance from selection and place it instead of selection
   also ask if a symbol (.sym) file needs to be created </pre>
   <li><kbd>       make_symbol</kbd></li><pre>
   From current schematic (circuit.sch) create a symbol (circuit.sym) 
@@ -1115,6 +1112,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
   <li><kbd>       zoom_selected</kbd></li><pre>
   Zoom to selection </pre>
 
+
+
  </ul>
 
 

src/scheduler.c

@@ -1858,6 +1858,40 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
       else if(argc==2 && errfp != stderr) { fclose(errfp); errfp=stderr; }
     }
 
+    /* logic_get net_name
+     *   Get logic state of net named 'net_name'
+     *   Returns 0, 1, 2, 3 for logic levels 0, 1, X, Z or nothing if no net found.
+     */
+    else if(!strcmp(argv[1], "logic_get"))
+    {
+      static char s[2]=".";
+      Tcl_ResetResult(interp);
+      if(argc > 2) {
+        Hilight_hashentry  *entry;
+        entry = bus_hilight_hash_lookup(argv[2], 0, XLOOKUP);
+        if(entry) {
+          switch(entry->value) {
+            case -5:
+            s[0] = '1';
+            break;
+            case -12:
+            s[0] = '0';
+            break;
+            case -1:
+            s[0] = '2';
+            break;
+            case -13:
+            s[0] = '3';
+            break;
+            default:
+            s[0] = '2';
+            break;
+          }
+          Tcl_SetResult(interp, s, TCL_VOLATILE);
+        }
+      }
+    }
+
     /* logic_set n num
      *   Set selected nets, net labels or pins to logic level 'n' 'num' times.
      *   'n': 
@@ -1882,6 +1916,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
     else { cmd_found = 0;}
     break;
     case 'm': /*----------------------------------------------*/
+    /* make_sch
+     *   Make a schematic from selected symbol */
     if(!strcmp(argv[1], "make_sch")) /* make schematic from selected symbol 20171004 */
     {
       create_sch_from_sym();
@@ -1889,7 +1925,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
     }
 
     /* make_sch_from_sel 
-     *   create an LCC instance from selection and place it instead of selection
+     *   Create an LCC instance from selection and place it instead of selection
      *   also ask if a symbol (.sym) file needs to be created */
     else if(!strcmp(argv[1], "make_sch_from_sel"))
     {