allow Shift-T command (toggle spice_ignore attribute) to cycle through ignore-shorted-unset on selected elements
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parent
0e53359ee0
commit
724c264c9d
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@ -1909,8 +1909,10 @@ void copy_symbol(xSymbol *dest_sym, xSymbol *src_sym)
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void toggle_ignore(void)
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{
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int i, n, first = 1, remove = 0;
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int i, n, first = 1;
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char *attr;
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int flag = 0; /* 1: spice_ignore=true, 2: spice_ignore=short */
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const char *spice_ignore_str;
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if(xctx->netlist_type == CAD_VERILOG_NETLIST) attr="verilog_ignore";
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else if(xctx->netlist_type == CAD_VHDL_NETLIST) attr="vhdl_ignore";
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else if(xctx->netlist_type == CAD_TEDAX_NETLIST) attr="tedax_ignore";
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@ -1925,12 +1927,22 @@ void toggle_ignore(void)
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xctx->push_undo();
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first = 0;
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}
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remove = 0;
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if(!strboolcmp(get_tok_value(xctx->inst[i].prop_ptr, attr, 0), "true")) remove = 1;
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if(remove) {
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my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, NULL));
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} else {
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flag = 0;
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spice_ignore_str = get_tok_value(xctx->inst[i].prop_ptr, attr, 0);
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if(!strcmp(spice_ignore_str, "short")) flag = 2;
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else if(!strboolcmp(spice_ignore_str, "true")) flag = 1;
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if(flag == 0) flag = 1;
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else if(flag == 1) flag = 2;
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else flag = 0;
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if(flag == 1) {
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my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, "true"));
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} else if(flag == 2) {
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my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, "short"));
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} else {
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my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, NULL));
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}
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set_inst_flags(&xctx->inst[i]);
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set_modify(1);
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