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xschem
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do not create nets for devices that have *_ignore=true attribute set, this generates false warnings about undriven nets.

This commit is contained in:
stefan schippers 2023-06-30 08:29:11 +02:00
parent f2812e1444
commit 6755975369
6 changed files with 46 additions and 41 deletions
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17
src/netlist.c
View File

@ -595,6 +595,7 @@ static void name_generics()
dbg(2, "name_generics(): naming generics from attached labels\n");
if(for_netlist) for (i=0;i<instances; ++i) { /* ... assign node fields on all (non label) instances */
if(inst[i].ptr<0) continue;
if(skip_instance(i, 0, netlist_lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(inst[i].ptr+ xctx->sym)->type);
if(type && !IS_LABEL_OR_PIN(type) ) {
if((generic_rects = (inst[i].ptr+ xctx->sym)->rects[GENERICLAYER]) > 0) {
@ -677,7 +678,7 @@ static void set_inst_node(int i, int j, const char *node)
dbg(1, "set_inst_node(): inst %s pin %d <-- %s\n", inst[i].instname, j, node);
expandlabel(inst[i].instname, &inst_mult);
my_strdup(_ALLOC_ID_, &inst[i].node[j], node);
skip = skip_instance(i, netlist_lvs_ignore);
skip = skip_instance(i, 1, netlist_lvs_ignore);
if(!for_netlist || skip) {
bus_node_hash_lookup(inst[i].node[j],"", XINSERT, 0,"","","","");
} else {
@ -852,17 +853,17 @@ static int skip_instance2(int i, int lvs_ignore, int mask)
return skip;
}
int skip_instance(int i, int lvs_ignore)
int skip_instance(int i, int skip_short, int lvs_ignore)
{
int skip = 0;
if(xctx->netlist_type == CAD_SPICE_NETLIST)
skip = skip_instance2(i, lvs_ignore, SPICE_SHORT | SPICE_IGNORE);
skip = skip_instance2(i, lvs_ignore, (skip_short ? SPICE_SHORT : 0) | SPICE_IGNORE);
else if(xctx->netlist_type == CAD_VERILOG_NETLIST)
skip = skip_instance2(i, lvs_ignore, VERILOG_SHORT | VERILOG_IGNORE);
skip = skip_instance2(i, lvs_ignore, (skip_short ? VERILOG_SHORT : 0) | VERILOG_IGNORE);
else if(xctx->netlist_type == CAD_VHDL_NETLIST)
skip = skip_instance2(i, lvs_ignore, VHDL_SHORT | VHDL_IGNORE);
skip = skip_instance2(i, lvs_ignore, (skip_short ? VHDL_SHORT : 0) | VHDL_IGNORE);
else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
skip = skip_instance2(i, lvs_ignore, TEDAX_SHORT | TEDAX_IGNORE);
skip = skip_instance2(i, lvs_ignore, (skip_short ? TEDAX_SHORT : 0) | TEDAX_IGNORE);
else skip = 0;
dbg(1, "skip_instance(): instance %d skip=%d\n", i, skip);
@ -1060,6 +1061,7 @@ static int name_nodes_of_pins_labels_and_propagate()
for (i=0;i<instances; ++i) {
/* name ipin opin label node fields from prop_ptr attributes */
if(inst[i].ptr<0) continue;
if(skip_instance(i, 0, netlist_lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(inst[i].ptr+ xctx->sym)->type);
if(print_erc && (!inst[i].instname || !inst[i].instname[0]) &&
!get_tok_value((inst[i].ptr+ xctx->sym)->templ, "name", 0)[0]
@ -1087,6 +1089,7 @@ static int name_nodes_of_pins_labels_and_propagate()
xctx->hilight_nets=1;
}
if(type && inst[i].node && IS_LABEL_OR_PIN(type) ) { /* instance must have a pin! */
#if 0
if(for_netlist) {
/* 20150918 skip labels / pins if ignore property specified on instance */
if( xctx->netlist_type == CAD_VERILOG_NETLIST && (inst[i].flags & VERILOG_IGNORE)) continue;
@ -1095,6 +1098,7 @@ static int name_nodes_of_pins_labels_and_propagate()
if( xctx->netlist_type == CAD_TEDAX_NETLIST && (inst[i].flags & TEDAX_IGNORE)) continue;
if( netlist_lvs_ignore && (inst[i].flags & LVS_IGNORE_OPEN)) continue;
}
#endif
port=0;
my_strdup2(_ALLOC_ID_, &dir, "");
if(strcmp(type,"label")) { /* instance is a port (not a label) */
@ -1210,6 +1214,7 @@ static int name_unlabeled_instances()
for (i = 0; i < instances; ++i)
{
if(!inst[i].node) continue;
if(skip_instance(i, 0, netlist_lvs_ignore)) continue;
if(inst[i].ptr != -1) {
rects=(inst[i].ptr+ xctx->sym)->rects[PINLAYER];
for(j = 0; j < rects; ++j) {

12
src/spice_netlist.c
View File

@ -166,7 +166,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
err |= traverse_node_hash(); /* print all warnings about unconnected floatings etc */
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type) ) {
if(top_sub && !flag) {
@ -187,7 +187,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
if(top_sub) fprintf(fd, "\n");
for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && !IS_LABEL_OR_PIN(type) ) {
@ -278,7 +278,7 @@ int global_spice_netlist(int global) /* netlister driver */
first = 0;
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=header' property */
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {
@ -307,7 +307,7 @@ int global_spice_netlist(int global) /* netlister driver */
/* print top subckt ipin/opins */
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
dbg(1, "global_spice_netlist(): |%s|\n", type);
/*
@ -329,7 +329,7 @@ int global_spice_netlist(int global) /* netlister driver */
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with no 'place=end' property
and no place=header */
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {
@ -463,7 +463,7 @@ int global_spice_netlist(int global) /* netlister driver */
if(!split_f) {
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=end' property */
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {

4
src/tedax_netlist.c
View File

@ -36,7 +36,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
if(!tedax_stop) {
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type) ) {
print_tedax_element(fd, i) ; /* this is the element line */
@ -44,7 +44,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
}
for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && !IS_LABEL_OR_PIN(type) ) {

22
src/verilog_netlist.c
View File

@ -45,7 +45,7 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
{
for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
dbg(2, "verilog_netlist(): into the netlisting loop\n");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type &&
@ -129,7 +129,7 @@ int global_verilog_netlist(int global) /* netlister driver */
fmt_attr = xctx->format ? xctx->format : "verilog_format";
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
@ -159,7 +159,7 @@ int global_verilog_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"opin"))==0)
{
@ -173,7 +173,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"iopin"))==0)
{
@ -187,7 +187,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"ipin"))==0)
{
@ -215,7 +215,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level out pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"opin"))==0)
{
@ -234,7 +234,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"iopin"))==0)
{
@ -253,7 +253,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"ipin"))==0)
{
@ -275,7 +275,7 @@ int global_verilog_netlist(int global) /* netlister driver */
fprintf(fd,"---- begin user architecture code\n");
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@ -460,7 +460,7 @@ int verilog_block_netlist(FILE *fd, int i)
fmt_attr = xctx->format ? xctx->format : "verilog_format";
for(j=0;j<xctx->instances; ++j)
{
if(skip_instance(j, lvs_ignore)) continue;
if(skip_instance(j, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[j].ptr+ xctx->sym)->type);
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
@ -560,7 +560,7 @@ int verilog_block_netlist(FILE *fd, int i)
err |= verilog_netlist(fd, verilog_stop);
fprintf(fd,"---- begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, lvs_ignore)) continue;
if(skip_instance(l, 1, lvs_ignore)) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;

30
src/vhdl_netlist.c
View File

@ -39,7 +39,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
fprintf(fd, "//// begin user declarations\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore)) continue;
if(skip_instance(l, 1, lvs_ignore)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if(!strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "arch_declarations") )
@ -55,7 +55,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
fprintf(fd, "//// begin user attributes\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore)) continue;
if(skip_instance(l, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"attributes"))==0)
{
@ -70,7 +70,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
{
for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
{ /* dont print elements with vhdl_ignore=true set in symbol */
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
dbg(2, "vhdl_netlist(): into the netlisting loop\n");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type &&
@ -152,7 +152,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level packages\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"package"))==0)
{
@ -167,7 +167,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level use statements\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"use"))==0)
{
@ -232,7 +232,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -249,7 +249,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -266,7 +266,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -284,7 +284,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level port attributes\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"port_attributes"))==0)
{
@ -363,7 +363,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
fprintf(fd,"//// begin user architecture code\n");
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore)) continue;
if(skip_instance(i, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@ -540,7 +540,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): packages\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore)) continue;
if(skip_instance(l, 1, lvs_ignore)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "package") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
@ -549,7 +549,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): use statements\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore)) continue;
if(skip_instance(l, 1, lvs_ignore)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "use") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
@ -591,7 +591,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): port attributes\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore)) continue;
if(skip_instance(l, 1, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"port_attributes"))==0)
{
@ -626,7 +626,7 @@ int vhdl_block_netlist(FILE *fd, int i)
found=0;
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore)) continue;
if(skip_instance(l, 1, lvs_ignore)) continue;
if(!xctx->x_strcmp(xctx->sym[j].name, tcl_hook2(xctx->inst[l].name)))
{
found=1; break;
@ -672,7 +672,7 @@ int vhdl_block_netlist(FILE *fd, int i)
fprintf(fd,"//// begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, lvs_ignore)) continue;
if(skip_instance(l, 1, lvs_ignore)) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;

2
src/xschem.h
View File

@ -1539,7 +1539,7 @@ extern void display_hilights(int what, char **str);
extern void redraw_hilights(int clear);
extern void set_tcl_netlist_type(void);
extern int prepare_netlist_structs(int for_netlist);
extern int skip_instance(int i, int lvs_ignore);
extern int skip_instance(int i, int skip_short, int lvs_ignore);
extern int shorted_instance(int i, int lvs_ignore);
extern int compare_schematics(const char *filename);
extern int warning_overlapped_symbols(int sel);