make @spice_get_current work for pnp and npn symbols
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parent
954d10eb25
commit
6682965dba
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@ -4001,6 +4001,8 @@ const char *translate(int inst, const char* s)
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dbg(1, "prefix=%c, path=%s\n", prefix, path);
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vsource = (prefix == 'v') || (prefix == 'e');
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s.%s)", prefix, path, instname, dev);
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else if(prefix == 'q')
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my_snprintf(fqdev, len, "i(@%c.%s%s.%s[ic])", prefix, path, instname, dev);
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else if(prefix == 'd' || prefix == 'm')
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my_snprintf(fqdev, len, "i(@%c.%s%s.%s[id])", prefix, path, instname, dev);
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else if(prefix == 'i')
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@ -4132,11 +4134,13 @@ const char *translate(int inst, const char* s)
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int vsource = (prefix == 'v') || (prefix == 'e');
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if(path[0]) {
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s)", prefix, path, dev);
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else if(prefix=='q') my_snprintf(fqdev, len, "i(@%c.%s%s[ic])", prefix, path, dev);
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else if(prefix=='d' || prefix == 'm') my_snprintf(fqdev, len, "i(@%c.%s%s[id])", prefix, path, dev);
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else if(prefix=='i') my_snprintf(fqdev, len, "i(@%c.%s%s[current])", prefix, path, dev);
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else my_snprintf(fqdev, len, "i(@%c.%s%s[i])", prefix, path, dev);
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} else {
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if(vsource) my_snprintf(fqdev, len, "i(%s)", dev);
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else if(prefix == 'q') my_snprintf(fqdev, len, "i(@%s[ic])", dev);
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else if(prefix == 'd' || prefix == 'm') my_snprintf(fqdev, len, "i(@%s[id])", dev);
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else if(prefix == 'i') my_snprintf(fqdev, len, "i(@%s[current])", dev);
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else my_snprintf(fqdev, len, "i(@%s[i])", dev);
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -57,3 +57,4 @@ T {@#1:pinnumber} -5 6.25 0 1 0.2 0.2 {layer=13}
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T {@#0:net_name} 25 -33.75 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#2:net_name} 25 23.75 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#1:net_name} -6.25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance}
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T {@spice_get_current} 40 -22.5 0 0 0.2 0.2 {layer=17}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -55,3 +55,4 @@ T {@#1:pinnumber} -5 6.25 0 1 0.2 0.2 {layer=13}
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T {@#2:net_name} 25 -33.75 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#0:net_name} 25 23.75 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#1:net_name} -6.25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance}
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T {@spice_get_current} 40 11.25 0 0 0.2 0.2 {layer=17}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -25,15 +25,15 @@ V {}
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S {}
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E {}
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B 2 10 -270 390 -110 {flags=graph
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y1=-5400
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y2=5400
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y1=-6800
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y2=6800
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=k
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x1=0.000952652
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x2=0.000957538
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x1=4e-10
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x2=0.001
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divx=5
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subdivx=1
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node=hv
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@ -42,15 +42,15 @@ dataset=0
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unitx=u
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}
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B 2 10 -440 390 -280 {flags=graph
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y1=-0.9
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y1=-0.8
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y2=13
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=0.000952652
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x2=0.000957538
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x1=4e-10
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x2=0.001
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divx=5
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subdivx=1
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@ -130,12 +130,12 @@ N 860 -610 860 -600 {lab=HV}
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N 880 -610 880 -600 {lab=HV}
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N 860 -620 860 -610 {lab=HV}
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N 880 -620 880 -610 {lab=HV}
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N 810 -430 810 -400 {lab=#net1}
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N 810 -490 870 -490 {lab=HV}
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N 790 -430 790 -400 {lab=#net1}
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N 790 -490 870 -490 {lab=HV}
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N 580 -430 580 -400 {lab=#net2}
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N 520 -430 520 -340 {lab=#net3}
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N 520 -340 720 -340 {lab=#net3}
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N 810 -340 870 -340 {lab=FB}
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N 790 -340 870 -340 {lab=FB}
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N 520 -490 580 -490 {lab=VCC}
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N 580 -680 580 -490 {lab=VCC}
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N 870 -530 870 -490 {lab=HV}
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@ -158,7 +158,7 @@ C {code.sym} 1140 -170 0 0 {
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name=STIMULI
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value=".option SCALE=1e-6 PARHIER=LOCAL RUNLVL=6 post MODMONTE=1
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.option sampling_method = SRS
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.option method=gear
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.option method=gear savecurrents
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vvss vss 0 dc 0
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.save all
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@ -199,9 +199,9 @@ C {lab_pin.sym} 870 -560 0 1 {name=p4 lab=HV}
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C {capa.sym} 1010 -450 0 0 {name=C1 m=1 value=1p}
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C {lab_pin.sym} 1010 -250 0 0 {name=p3 lab=VSS}
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C {ind.sym} 580 -460 2 1 {name=L1 value=9.8u}
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C {ind.sym} 810 -460 0 1 {name=L2 value=9.1m}
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C {ind.sym} 790 -460 0 1 {name=L2 value=9.1m}
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C {k.sym} 700 -460 0 0 {name=K0 K=0.15 L1=L1 L2=L2}
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C {res.sym} 810 -370 0 0 {name=R0 m=1 value=.32}
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C {res.sym} 790 -370 0 0 {name=R0 m=1 value=.32}
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C {capa.sym} 870 -460 0 1 {name=C0 m=1 value=4.1p}
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C {res.sym} 580 -370 0 1 {name=R3 m=1 value=0.22}
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C {capa.sym} 520 -460 0 0 {name=C5 m=1 value=13p}
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