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recognize \r\n sequences on windows rawfiles in "Binary:" lines, just in case ngspice developers want to add it someday. Quote ROUT ('ROUT') values for output resistors in ngspice_logic gates

This commit is contained in:
Stefan Frederik 2022-07-28 00:36:09 +02:00
parent 5af2b8eb7a
commit 56d3d8f5f3
10 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/save.c
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@ -309,7 +309,7 @@ static int read_dataset(FILE *fd)
"Use binary format in ngspice (set filetype=binary)}"); "Use binary format in ngspice (set filetype=binary)}");
return 0; return 0;
} }
if(!strcmp(line, "Binary:\n")) { if(!strcmp(line, "Binary:\n") || !strcmp(line, "Binary:\r\n")) {
int npoints = xctx->graph_npoints[xctx->graph_datasets]; int npoints = xctx->graph_npoints[xctx->graph_datasets];
if(xctx->graph_sim_type) { if(xctx->graph_sim_type) {
done_header = 1; done_header = 1;

2
xschem_library/ngspice/and3_ngspice.sch
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@ -18,7 +18,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((min(V(C1),min(
C {lab_pin.sym} 310 -400 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 310 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 580 -400 1 0 {name=R1 C {res.sym} 580 -400 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}

2
xschem_library/ngspice/and_ngspice.sch
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@ -17,7 +17,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((min(V(A1),V(B1
C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 580 -400 1 0 {name=R1 C {res.sym} 580 -400 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}

2
xschem_library/ngspice/buf_ngspice.sch
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@ -17,7 +17,7 @@ C {bsource.sym} 470 -400 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((V(A1)-VCC/2)*1
C {lab_pin.sym} 320 -470 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 320 -470 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 470 -320 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 470 -320 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 570 -470 1 0 {name=R1 C {res.sym} 570 -470 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}

2
xschem_library/ngspice/inv_ngspice.sch
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@ -17,7 +17,7 @@ C {bsource.sym} 470 -400 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1-tanh((V(A1)-VCC/2)*1
C {lab_pin.sym} 320 -470 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 320 -470 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 470 -320 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 470 -320 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 570 -470 1 0 {name=R1 C {res.sym} 570 -470 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}

2
xschem_library/ngspice/nand_ngspice.sch
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@ -17,7 +17,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1-tanh((min(V(A1),V(B1
C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 580 -400 1 0 {name=R1 C {res.sym} 580 -400 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}

2
xschem_library/ngspice/nor_ngspice.sch
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@ -17,7 +17,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1-tanh((max(V(A1),V(B1
C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 580 -400 1 0 {name=R1 C {res.sym} 580 -400 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}

2
xschem_library/ngspice/or_ngspice.sch
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@ -17,7 +17,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((max(V(A1),V(B1
C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 580 -400 1 0 {name=R1 C {res.sym} 580 -400 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}

2
xschem_library/ngspice/xnor_ngspice.sch
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@ -17,7 +17,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1-tanh((abs(V(A1)-V(B1
C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 580 -400 1 0 {name=R1 C {res.sym} 580 -400 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}

2
xschem_library/ngspice/xor_ngspice.sch
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@ -17,7 +17,7 @@ C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((abs(V(A1)-V(B1
C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
C {res.sym} 580 -400 1 0 {name=R1 C {res.sym} 580 -400 1 0 {name=R1
value=ROUT value='ROUT'
footprint=1206 footprint=1206
device=resistor device=resistor
m=1} m=1}