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add option -noalert to `xschem netlist` command, update `proc cellview`

This commit is contained in:
stefan schippers 2025-01-19 23:29:41 +01:00
parent 16121b6e07
commit 4f31c024c8
10 changed files with 107 additions and 62 deletions
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11
src/actions.c
View File

@ -537,6 +537,10 @@ const char *get_file_path(char *f)
* -1 : user cancel
* 0 : file not saved due to errors or per user request
* confirm:
* 0 : do not ask user to save
* 1 : ask user to save
* fast:
* passed to save_schematic
*/
int save(int confirm, int fast)
{
@ -544,8 +548,11 @@ int save(int confirm, int fast)
char *name = xctx->sch[xctx->currsch];
int force = 0;
/* current schematic exists on disk ... */
if(!stat(name, &buf)) {
/* ... and modification time on disk has changed since file loaded ... */
if(xctx->time_last_modify && xctx->time_last_modify != buf.st_mtime) {
/* ... so force a save */
force = 1;
confirm = 0;
}
@ -2073,8 +2080,8 @@ void get_additional_symbols(int what)
}
}
/* fallback = 1: if schematic attribute is set but file not existing fallback
* if inst == -1 use only symbol reference
* to defaut symbol schematic (symname.sym -> symname.sch) */
* to defaut symbol schematic (symname.sym -> symname.sch)
* if inst == -1 use only symbol reference */
void get_sch_from_sym(char *filename, xSymbol *sym, int inst, int fallback)
{
char *sch = NULL;

16
src/callback.c
View File

@ -3716,13 +3716,13 @@ int rstate; /* (reduced state, without ShiftMask) */
if(set_netlist_dir(0, NULL)) {
dbg(1, "callback(): -------------\n");
if(xctx->netlist_type == CAD_SPICE_NETLIST)
err = global_spice_netlist(1);
err = global_spice_netlist(1, 1);
else if(xctx->netlist_type == CAD_VHDL_NETLIST)
err = global_vhdl_netlist(1);
err = global_vhdl_netlist(1, 1);
else if(xctx->netlist_type == CAD_VERILOG_NETLIST)
err = global_verilog_netlist(1);
err = global_verilog_netlist(1, 1);
else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
err = global_tedax_netlist(1);
err = global_tedax_netlist(1, 1);
else
tcleval("tk_messageBox -type ok -parent [xschem get topwindow] "
"-message {Please Set netlisting mode (Options menu)}");
@ -3757,13 +3757,13 @@ int rstate; /* (reduced state, without ShiftMask) */
if( set_netlist_dir(0, NULL) ) {
dbg(1, "callback(): -------------\n");
if(xctx->netlist_type == CAD_SPICE_NETLIST)
err = global_spice_netlist(0);
err = global_spice_netlist(0, 1);
else if(xctx->netlist_type == CAD_VHDL_NETLIST)
err = global_vhdl_netlist(0);
err = global_vhdl_netlist(0, 1);
else if(xctx->netlist_type == CAD_VERILOG_NETLIST)
err = global_verilog_netlist(0);
err = global_verilog_netlist(0, 1);
else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
err = global_tedax_netlist(0);
err = global_tedax_netlist(0, 1);
else
tcleval("tk_messageBox -type ok -parent [xschem get topwindow] "
"-message {Please Set netlisting mode (Options menu)}");

13
src/scheduler.c
View File

@ -3200,7 +3200,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
hilight_net_pin_mismatches();
}
/* netlist [-messages | -erc | -nohier] [filename]
/* netlist [-noalert -messages | -erc | -nohier] [filename]
* do a netlist of current schematic in currently defined netlist format
* if 'filename'is given use specified name for the netlist
* if 'filename' contains path components place the file in specified path location.
@ -3219,6 +3219,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
int err = 0;
int hier_netlist = 1;
int i, messages = 0;
int alert = 1;
int erc = 0;
const char *fname = NULL;
const char *path;
@ -3235,6 +3236,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
messages = 1;
} else if(!strcmp(argv[i], "-erc")) {
erc = 1;
} else if(!strcmp(argv[i], "-noalert")) {
alert = 0;
} else if(!strcmp(argv[i], "-nohier")) {
hier_netlist = 0;
}
@ -3255,13 +3258,13 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(set_netlist_dir(0, NULL) ) {
done_netlist = 1;
if(xctx->netlist_type == CAD_SPICE_NETLIST)
err = global_spice_netlist(hier_netlist); /* 1 means global netlist */
err = global_spice_netlist(hier_netlist, alert); /* 1 means global netlist */
else if(xctx->netlist_type == CAD_VHDL_NETLIST)
err = global_vhdl_netlist(hier_netlist);
err = global_vhdl_netlist(hier_netlist, alert);
else if(xctx->netlist_type == CAD_VERILOG_NETLIST)
err = global_verilog_netlist(hier_netlist);
err = global_verilog_netlist(hier_netlist, alert);
else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
global_tedax_netlist(hier_netlist);
global_tedax_netlist(hier_netlist, alert);
else
if(has_x) tcleval("tk_messageBox -type ok -parent [xschem get topwindow] "
"-message {Please Set netlisting mode (Options menu)}");

14
src/spice_netlist.c
View File

@ -247,7 +247,8 @@ static int spice_netlist(FILE *fd, int spice_stop )
return err;
}
int global_spice_netlist(int global) /* netlister driver */
/* alert: if set show alert if file missing */
int global_spice_netlist(int global, int alert) /* netlister driver */
{
int err = 0;
int first;
@ -478,12 +479,12 @@ int global_spice_netlist(int global) /* netlister driver */
if(strcmp(get_tok_value(xctx->sym[i].prop_ptr, "default_schematic", 0), "ignore"))
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
if( split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_netlist",0),"true")==0 )
err |= vhdl_block_netlist(fd, i);
err |= vhdl_block_netlist(fd, i, alert);
else if(split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_netlist",0),"true")==0 )
err |= verilog_block_netlist(fd, i);
err |= verilog_block_netlist(fd, i, alert);
else
if( strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_primitive",0),"true") )
err |= spice_block_netlist(fd, i);
err |= spice_block_netlist(fd, i, alert);
}
}
}
@ -593,7 +594,8 @@ int global_spice_netlist(int global) /* netlister driver */
return err;
}
int spice_block_netlist(FILE *fd, int i)
/* alert: if set show alert if file missing */
int spice_block_netlist(FILE *fd, int i, int alert)
{
int err = 0;
int spice_stop=0;
@ -667,7 +669,7 @@ int spice_block_netlist(FILE *fd, int i)
my_free(_ALLOC_ID_, &extra);
fprintf(fd, "\n");
spice_stop ? load_schematic(0,filename, 0, 1) : load_schematic(1,filename, 0, 1);
spice_stop ? load_schematic(0,filename, 0, alert) : load_schematic(1,filename, 0, alert);
get_additional_symbols(1);
err |= spice_netlist(fd, spice_stop); /* 20111113 added spice_stop */
err |= warning_overlapped_symbols(0);

8
src/tedax_netlist.c
View File

@ -69,7 +69,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
return err;
}
static int tedax_block_netlist(FILE *fd, int i)
static int tedax_block_netlist(FILE *fd, int i, int alert)
{
int err = 0;
int tedax_stop=0;
@ -107,7 +107,7 @@ static int tedax_block_netlist(FILE *fd, int i)
fprintf(fd, "%s", get_sym_template(xctx->sym[i].templ, extra));
my_free(_ALLOC_ID_, &extra);
fprintf(fd, "\n");
load_schematic(1,filename, 0, 1);
load_schematic(1,filename, 0, alert);
get_additional_symbols(1);
err |= tedax_netlist(fd, tedax_stop);
xctx->netlist_count++;
@ -121,7 +121,7 @@ static int tedax_block_netlist(FILE *fd, int i)
return err;
}
int global_tedax_netlist(int global) /* netlister driver */
int global_tedax_netlist(int global, int alert) /* netlister driver */
{
int err = 0;
FILE *fd;
@ -232,7 +232,7 @@ int global_tedax_netlist(int global) /* netlister driver */
* will not be processed by *_block_netlist() */
if(strcmp(get_tok_value(xctx->sym[i].prop_ptr, "default_schematic", 0), "ignore"))
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
err |= tedax_block_netlist(fd, i);
err |= tedax_block_netlist(fd, i, alert);
}
}
}

12
src/verilog_netlist.c
View File

@ -75,7 +75,7 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
return err;
}
int global_verilog_netlist(int global) /* netlister driver */
int global_verilog_netlist(int global, int alert) /* netlister driver */
{
int err = 0;
FILE *fd;
@ -350,11 +350,11 @@ int global_verilog_netlist(int global) /* netlister driver */
if(strcmp(get_tok_value(xctx->sym[i].prop_ptr, "default_schematic", 0), "ignore"))
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
if( split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_netlist",0),"true")==0 )
err |= vhdl_block_netlist(fd, i);
err |= vhdl_block_netlist(fd, i, alert);
else if(split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_netlist",0),"true")==0 )
err |= spice_block_netlist(fd, i);
err |= spice_block_netlist(fd, i, alert);
else if( strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_primitive",0), "true"))
err |= verilog_block_netlist(fd, i);
err |= verilog_block_netlist(fd, i, alert);
}
}
}
@ -413,7 +413,7 @@ int global_verilog_netlist(int global) /* netlister driver */
}
int verilog_block_netlist(FILE *fd, int i)
int verilog_block_netlist(FILE *fd, int i, int alert)
{
int err = 0;
int j, l, tmp;
@ -469,7 +469,7 @@ int verilog_block_netlist(FILE *fd, int i)
my_strdup(_ALLOC_ID_, &extra, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
my_strdup(_ALLOC_ID_, &extra2, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
fprintf(fd, "// sch_path: %s\n", sanitized_abs_sym_path(filename, ""));
verilog_stop? load_schematic(0,filename, 0, 1) : load_schematic(1,filename, 0, 1);
verilog_stop? load_schematic(0,filename, 0, alert) : load_schematic(1,filename, 0, alert);
get_additional_symbols(1);
/* print verilog timescale and preprocessor directives 10102004 */
fmt_attr = xctx->format ? xctx->format : "verilog_format";

14
src/vhdl_netlist.c
View File

@ -101,7 +101,8 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
return err;
}
int global_vhdl_netlist(int global) /* netlister driver */
/* alert: if set show alert if file missing */
int global_vhdl_netlist(int global, int alert) /* netlister driver */
{
int err = 0;
FILE *fd;
@ -439,11 +440,11 @@ int global_vhdl_netlist(int global) /* netlister driver */
if(strcmp(get_tok_value(xctx->sym[i].prop_ptr, "default_schematic", 0), "ignore"))
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
if( split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_netlist",0),"true")==0 )
err |= verilog_block_netlist(fd, i);
err |= verilog_block_netlist(fd, i, alert);
else if( split_f && strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_netlist",0),"true")==0 )
err |= spice_block_netlist(fd, i);
err |= spice_block_netlist(fd, i, alert);
else if( strboolcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_primitive",0),"true"))
err |= vhdl_block_netlist(fd, i);
err |= vhdl_block_netlist(fd, i, alert);
}
}
}
@ -499,7 +500,8 @@ int global_vhdl_netlist(int global) /* netlister driver */
return err;
}
int vhdl_block_netlist(FILE *fd, int i)
/* alert: if set show alert if file missing */
int vhdl_block_netlist(FILE *fd, int i, int alert)
{
int err = 0;
int j,k,l, tmp, found;
@ -550,7 +552,7 @@ int vhdl_block_netlist(FILE *fd, int i)
} else {
Int_hashtable table = {NULL, 0};
fprintf(fd, "-- sch_path: %s\n", sanitized_abs_sym_path(filename, ""));
load_schematic(1,filename, 0, 1);
load_schematic(1,filename, 0, alert);
get_additional_symbols(1);
dbg(1, "vhdl_block_netlist(): packages\n");
for(l=0;l<xctx->instances; ++l)

8
src/xinit.c
View File

@ -2978,13 +2978,13 @@ int Tcl_AppInit(Tcl_Interp *inter)
fprintf(errfp, "xschem: flat netlist requested\n");
}
if(xctx->netlist_type == CAD_SPICE_NETLIST)
global_spice_netlist(1); /* 1 means global netlist */
global_spice_netlist(1, 1); /* 1 means global netlist */
else if(xctx->netlist_type == CAD_VHDL_NETLIST)
global_vhdl_netlist(1); /* 1 means global netlist */
global_vhdl_netlist(1, 1); /* 1 means global netlist */
else if(xctx->netlist_type == CAD_VERILOG_NETLIST)
global_verilog_netlist(1); /* 1 means global netlist */
global_verilog_netlist(1, 1); /* 1 means global netlist */
else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
global_tedax_netlist(1); /* 1 means global netlist */
global_tedax_netlist(1, 1); /* 1 means global netlist */
} else {
fprintf(errfp, "xschem: please set netlist_dir in xschemrc\n");
}

14
src/xschem.h
View File

@ -1473,13 +1473,13 @@ extern void store_arc(int pos, double x, double y, double r, double a, double b,
unsigned int rectcolor, unsigned short sel, char *prop_ptr);
extern void hier_psprint(char **res, int what);
extern int global_spice_netlist(int global);
extern int global_tedax_netlist(int global);
extern int global_vhdl_netlist(int global);
extern int global_verilog_netlist(int global);
extern int vhdl_block_netlist(FILE *fd, int i);
extern int verilog_block_netlist(FILE *fd, int i);
extern int spice_block_netlist(FILE *fd, int i);
extern int global_spice_netlist(int global, int alert);
extern int global_tedax_netlist(int global, int alert);
extern int global_vhdl_netlist(int global, int alert);
extern int global_verilog_netlist(int global, int alert);
extern int vhdl_block_netlist(FILE *fd, int i, int alert);
extern int verilog_block_netlist(FILE *fd, int i, int alert);
extern int spice_block_netlist(FILE *fd, int i, int alert);
extern void remove_symbols(void);
extern void remove_symbol(int i);
extern void clear_drawing(void);

59
src/xschem.tcl
View File

@ -1770,7 +1770,7 @@ proc simconf_add {tool} {
############ cellview
# proc cellview prints symbol bindings (default binding or "schematic" attr in symbol)
# of all symbols used in current and sub schematics.
proc cellview_setlabels {w symbol sym_sch sym_spice_sym_def derived_symbol} {
proc cellview_setlabels {w symbol derived_symbol} {
global dark_gui_colorscheme
if {$dark_gui_colorscheme} {
set instfg orange1
@ -1783,6 +1783,12 @@ proc cellview_setlabels {w symbol sym_sch sym_spice_sym_def derived_symbol} {
set symbg SeaGreen1
set missingbg IndianRed1
}
set current [xschem get current_name]
set sym_spice_sym_def [xschem getprop symbol $symbol spice_sym_def 2]
set abs_sch [xschem get_sch_from_sym -1 $symbol]
set sym_sch [rel_sym_path $abs_sch]
set default_sch [add_ext $symbol .sch]
set new_sch [$w get]
$w configure -fg [option get . foreground {}]
$w configure -bg [option get . background {}]
if { $derived_symbol} {
@ -1790,18 +1796,31 @@ proc cellview_setlabels {w symbol sym_sch sym_spice_sym_def derived_symbol} {
} elseif {$sym_spice_sym_def ne {} } {
$w configure -fg $symfg
}
puts ===============
puts sym_sch=$sym_sch
puts symbol=$symbol
if { $sym_spice_sym_def eq {}} {
if { ![file exists [abs_sym_path [$w get]]] } {
$w configure -bg $missingbg
}
}
puts ===============
if {$sym_sch ne $new_sch && $sym_spice_sym_def eq {}} {
puts "Changing schematic attribute in symbol"
xschem load $symbol noundoreset nodraw
set oldprop [xschem get schsymbolprop]
set newprop [xschem subst_tok $oldprop schematic $new_sch]
xschem set schsymbolprop $newprop
xschem set_modify 3 ;# set only modified flag to force a save, do not update window/tab titles
xschem save fast
xschem load $current noundoreset nodraw
xschem reload_symbols ;# update in-memory symbol data
}
puts sym_sch=$sym_sch
puts default_sch=$default_sch
puts new_sch=$new_sch
puts symbol=$symbol
}
proc cellview_edit_item {w sym_spice_sym_def} {
proc cellview_edit_item {symbol w} {
set sym_spice_sym_def [xschem getprop symbol $symbol spice_sym_def 2]
if {[xschem is_generator [$w get]]} {
set f [$w get]
regsub {\(.*} $f {} f
@ -1809,7 +1828,21 @@ proc cellview_edit_item {w sym_spice_sym_def} {
} elseif { $sym_spice_sym_def eq {}} {
xschem load_new_window [$w get]
} else {
editdata $sym_spice_sym_def {Symbol spice_sym_def attribute}
puts $symbol
set current [xschem get current_name]
set old_sym_def [xschem getprop symbol $symbol spice_sym_def 2]
set new_sym_def [editdata $sym_spice_sym_def {Symbol spice_sym_def attribute}]
if {$new_sym_def ne $old_sym_def} {
xschem load $symbol noundoreset nodraw
set oldprop [xschem get schsymbolprop]
set newprop [xschem subst_tok $oldprop spice_sym_def $new_sym_def]
xschem set schsymbolprop $newprop
xschem set_modify 3 ;# set only modified flag to force a save, do not update window/tab titles
xschem save fast
puts "$symbol: updated spice_sym_def attribute"
xschem load $current noundoreset nodraw
xschem reload_symbols ;# update in-memory symbol data
}
}
}
@ -1848,7 +1881,7 @@ proc cellview {{derived_symbols {}}} {
xschem reload_symbols ;# purge unused symbols
set save_keep $keep_symbols
set keep_symbols 1 ;# keep all symbols when doing a hierarchic netlist
xschem netlist ;# traverse the hierarchy and retain all encountered symbols
xschem netlist -noalert;# traverse the hierarchy and retain all encountered symbols
set keep_symbols $save_keep
wm geometry .cv 800x200
update
@ -1899,7 +1932,7 @@ proc cellview {{derived_symbols {}}} {
button $sf.f$i.sym -text Sym -padx 4 -borderwidth 1 -pady 0 -font $font \
-command "cellview_edit_sym $sf.f$i.l"
button $sf.f$i.sch -text Sch -padx 4 -borderwidth 1 -pady 0 -font $font \
-command "cellview_edit_item $sf.f$i.s [list $sym_spice_sym_def]"
-command "cellview_edit_item $symbol $sf.f$i.s"
if {$sym_spice_sym_def eq {}} {
$sf.f$i.s insert 0 $sym_sch
} else {
@ -1916,20 +1949,18 @@ proc cellview {{derived_symbols {}}} {
set f [abs_sym_path [$sf.f$i.s get]]
} else {
set ff [split $sym_spice_sym_def \n]
puts ff=$ff
if {[llength $ff] > 5} {
set ff [lrange $ff 0 4]
lappend ff ...
}
set f [join $ff \n]
puts f=$f
}
balloon $sf.f$i.s $f
bind $sf.f$i.s <KeyRelease> "
cellview_setlabels %W [list $symbol] [list $sym_sch] [list $sym_spice_sym_def] $derived_symbol
cellview_setlabels %W [list $symbol] $derived_symbol
"
cellview_setlabels $sf.f$i.s $symbol $sym_sch $sym_spice_sym_def $derived_symbol
cellview_setlabels $sf.f$i.s $symbol $derived_symbol
pack $sf.f$i.l $sf.f$i.s -side left -fill x -expand 1
pack $sf.f$i.sch $sf.f$i.sym -side left
}
@ -2014,7 +2045,7 @@ proc traversal_setlabels {w parent_sch instname inst_sch sym_sch default_sch ins
}
# This proc traverses the hierarchy and prints all instances in design.
proc traversal {{only_subckts 0} {all_hierarchy 1}} {
proc traversal {{only_subckts 1} {all_hierarchy 1}} {
global keep_symbols traversal_cnt
set traversal_cnt 0
set save_keep $keep_symbols