Updated analyses library authorship info.

xschem_library/analyses/README.md

@@ -72,3 +72,8 @@ Nodesets and initial conditions specified with the `nodeset` and `ic` attributes
 A dcxf block runs the TF analysis. The value of the `in` attribute specifies the quoted name of the input source. This attribute is ignored in VACASK netlists because VACASK computes the transfer functions from all independent sources to the given output. 
 
 For the noise block the number of points per summary can be set with the `ptssum` attribute. This attribute is ignored in VACASK netlists. 
+
+
+# Credits
+
+The analyses library was created by Arpad Buermen. Send your comments to: arpad[dot]buermen[at]fe.uni-lj.si

xschem_library/analyses/ac.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/acxf.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/command_block.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/dc1d.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/dcinc.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/dcxf.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/demo.sch

@@ -1,4 +1,22 @@
-v {xschem version=3.4.8RC file_version=1.3}
+v {xschem version=3.4.8RC file_version=1.3
+*
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+}
 G {}
 K {}
 V {}

xschem_library/analyses/hb.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/lib_init.tcl

@@ -1,3 +1,20 @@
+# Analyses library for visual circuit analysis setup. 
+# Copyright (C) 2025 Arpad Buermen
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
 namespace eval ::analyses {
 
 # Parenthesize string if not empty

xschem_library/analyses/noise.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/op.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/postproc.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/sweep.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/tran.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/verbatim.sym

@@ -1,9 +1,7 @@
 v {xschem version=3.4.8RC file_version=1.3
 *
-* This file is part of XSCHEM,
-* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
-* simulation.
-* Copyright (C) 1998-2024 Stefan Frederik Schippers
+* Analyses library for visual circuit analysis setup. 
+* Copyright (C) 2025 Arpad Buermen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by

xschem_library/analyses/xschemrc

@@ -1,8 +1,22 @@
+# Sample xschemrc for analyses library
+# Analyses library for visual circuit analysis setup. 
+# Copyright (C) 2025 Arpad Buermen
+
 set netlist_dir $env(HOME)/.xschem/simulations
-set netlist_type spectre
-set editor {kwrite}
+# set editor {kwrite}
 
-set netlist_type spectre
-set netlist_show 1
+# set netlist_show 1
 
-source analyses.init.tcl
+# set netlist_type spice
+set letlist_type spectre
+
+#
+# Add this part to your xschemrc to make the analyses library work
+#
+append postinit_commands {
+  foreach i $pathlist {
+    if {![catch {source $i/lib_init.tcl} retval]} {
+      puts "Sourced library init file $i/lib_init.tcl"
+    } 
+  }
+}